Status handling for transfer of data blocks between a local side and a host side

Claim 1

An information handling system for transferring data blocks between a first processing side and a second processing side over an I/O expansion data bus, comprising: a host processing unit, a first memory accessible by said host processing unit including first memory portions for storing first data blocks involved in data block transfers between the first processing side and the second processing side; a transfer status queue memory portion including a plurality of status queue images, each status queue image storing a status information relating to a corresponding data block transfer; a local processing unit; a second memory accessible by the local processing unit including second memory portions for storing second data blocks involved in data block transfers between the first processing side and the second processing side, a Data Channel Block (DCB) memory portion comprising a plurality of DCB images wherein each of said DCB images stores: a first address information corresponding to a first memory portion involved in a data block transfer; and a second address information corresponding to a second memory portion involved in the data block transfer; a status queue register set programmable by said host processing unit before start of any data block transfer for setting a predefined address for the status queue memory portion and for storing a head pointer value pointing to a default status queue image indicating where a subsequent status information is to be stored and a tail pointer pointing to a default status queue image indicating from where a subsequent status information is to be retrieved; a first memory access controller responsive to said first address information for accessing a corresponding first memory portion; a second memory access controller responsive to said second address information for accessing the corresponding second memory portion; and a data transfer status controller which stores status queue images for a successful transfer as data is being transferred, includes hardware logic which monitors for errors during data transfer and is responsive to said data transfer queue register set for transferring a corresponding status queue image into the data transfer status queue memory portion upon completion of a data transfer without errors and includes hardware logic which detects the transfer of the status queue image into the status queue memory portion and responsively sends an interrupt to the host processor to indicate an unserviced status image, whereby status information is provided to the host processing unit without local processing unit intervention.