US5249284A
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US
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Method and system for maintaining data coherency between main and cache memories
Assignee: NCR Voyix Corp
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Filing: 1991-12-13
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Granted: 1993-09-28
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Expires: 2011-12-13
Abstract
Abstract A method and system of maintaining coherency for a data block transferred from a main memory to a cache memory. The data transfer is recorded in a tag register in the main memory. An overwrite of the data block is detected by comparing main memory data writes with the recorded transfer. The cache memory is only notified in the event an overwrite is detected. An invalid flag is then set in the cache.
Inventors
- 👤 William J. Kass
- 👤 Michael R. Hilley
- 👤 Lee W. Hoevel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:33
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0826; G06F2212/00; G06F2212/62; G06F2212/622
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
121 words
A method of maintaining coherency for a first data block transferred from a first memory to a second memory, wherein said first memory stores a plurality of data blocks, the method comprising: creating a tag register in said first memory having addressable locations corresponding to each data block in said first memory, each location having a one-to-one correspondence with a data block in said first memory; setting a tag bit in said tag register at a location corresponding to the address of said first data block; overwriting said first data block in the first memory with a second data block; detecting the overwriting of said first data block by examining the tag bit; and notifying said second memory of the overwriting.
Claim 2
Independent Claim
121 words
A method of maintaining coherency for a first data block transferred from a first memory to a second memory, wherein said first memory stores a plurality of data blocks, the method comprising: creating a tag register in said first memory having addressable locations corresponding to each data block in said first memory, each location having a one-to-one correspondence with a data block in said first memory; setting a tag bit in said tag register at a location corresponding to the address of said first data block; overwriting said first data block in the first memory with a second data block; detecting the overwriting of said first data block by examining the tag bit; and notifying said second memory of the overwriting.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein said detecting step includes: reading said register with the address of data written to said first memory.
Claim 4
Dependent Claim
19 words
The method of claim 2 further comprising: resetting said tag bit while notifying said second memory of said overwrite.
Claim 5
Dependent Claim
24 words
The method of claim 1 further comprising: setting an invalid flag in said second memory at a location corresponding to said overwritten data block.
Claim 6
Dependent Claim
44 words
The method of claim 1 wherein said first memory is connected to first and second busses, said second memory is connected to said first but not second bus, and wherein said data transfers to said first memory are received from said second data bus.
Claim 7
Dependent Claim
21 words
The method of claim 1 wherein said first memory is a main memory and said second memory is a cache memory.
Claim 8
Dependent Claim
27 words
The method of claim 6 wherein said cache memory is associated with a processor and wherein said notifying step includes: transmitting an interrupt signal to said processor.
Claim 9
Independent Claim
107 words
A method of maintaining coherency for a data block transferred from a main memory to a cache memory comprising: providing said main memory with a tag register; recording said transfer by setting a tag bit in said register at a location corresponding to the address of said data block; detecting an overwrite of said data block by reading said register with the address of data written to said main memory; notifying said cache memory of said overwrite; resetting said tag bit while notifying said cache memory of said overwrite; and setting an invalid flag in said cache memory at a location corresponding to said overwritten data block.
Claim 10
Independent Claim
107 words
A method of maintaining coherency for a data block transferred from a main memory to a cache memory comprising: providing said main memory with a tag register; recording said transfer by setting a tag bit in said register at a location corresponding to the address of said data block; detecting an overwrite of said data block by reading said register with the address of data written to said main memory; notifying said cache memory of said overwrite; resetting said tag bit while notifying said cache memory of said overwrite; and setting an invalid flag in said cache memory at a location corresponding to said overwritten data block.
Claim 11
Dependent Claim
63 words
The method of claim 8 wherein said main memory is connected to first and second busses, said cache memory is connected to said first but not second bus, said data transfers to said main memory are received from said second data bus, said cache memory is associated with a processor and wherein said notifying step includes: transmitting an interrupt signal to said processor.
Claim 12
Dependent Claim
12 words
The method of claim 9 wherein said cache is a write-through cache.
Claim 13
Independent Claim
174 words
A method for maintaining data coherency between a main memory connected to a plurality of busses and a plurality of cache memories connected to respective ones of said busses, wherein said main memory stores a plurality of data blocks, the method comprising: providing a register in said main memory having addressable locations corresponding to each data block in said main memory, each location having a one-to-one correspondence with a data block in said main memory, each location having a plurality of bit positions, and each position corresponding to a respective one of said busses; transferring a data block from said main memory to a first cache memory on a first bus; setting a tag bit in said register at a location corresponding to the transferred data block and at the bit position corresponding to said first bus; addressing said register with the address of data written to said main memory to determine if a tag bit is set indicating an overwrite of said transferred data block; and notifying said first cache of said overwrite.
Claim 14
Independent Claim
174 words
A method for maintaining data coherency between a main memory connected to a plurality of busses and a plurality of cache memories connected to respective ones of said busses, wherein said main memory stores a plurality of data blocks, the method comprising: providing a register in said main memory having addressable locations corresponding to each data block in said main memory, each location having a one-to-one correspondence with a data block in said main memory, each location having a plurality of bit positions, and each position corresponding to a respective one of said busses; transferring a data block from said main memory to a first cache memory on a first bus; setting a tag bit in said register at a location corresponding to the transferred data block and at the bit position corresponding to said first bus; addressing said register with the address of data written to said main memory to determine if a tag bit is set indicating an overwrite of said transferred data block; and notifying said first cache of said overwrite.
Claim 15
Dependent Claim
26 words
The method of claim 11 further comprising: setting an invalid flag in said first cache memory at a location corresponding to said overwritten first data block.
Claim 16
Dependent Claim
14 words
The method of claim 12 wherein said first cache memory is a write-through cache.
Claim 17
Dependent Claim
19 words
The method of claim 11 further comprising: resetting said tag bit while notifying said first cache of said overwrite.
Claim 18
Independent Claim
163 words
A method of maintaining data coherency between a main memory and a plurality of cache memories, wherein said main memory stores a plurality of data blocks, the method comprising: providing a register in said main memory having addressable locations corresponding to each data block in said main memory, each location having a one-to-one correspondence with a data block in said main memory, each location having a plurality of bit positions, and each position corresponding to a respective one of said cache memories; transferring a first data block from said main memory to a first of said cache memories; setting a first tag bit in said register at a location corresponding to the transferred data block and at the bit position corresponding to said first cache memory; addressing said register with the address of data written to said main memory to determine if a tag bit is set indicating an overwrite of said first data block; and notifying said first cache of an overwrite.
Claim 19
Independent Claim
163 words
A method of maintaining data coherency between a main memory and a plurality of cache memories, wherein said main memory stores a plurality of data blocks, the method comprising: providing a register in said main memory having addressable locations corresponding to each data block in said main memory, each location having a one-to-one correspondence with a data block in said main memory, each location having a plurality of bit positions, and each position corresponding to a respective one of said cache memories; transferring a first data block from said main memory to a first of said cache memories; setting a first tag bit in said register at a location corresponding to the transferred data block and at the bit position corresponding to said first cache memory; addressing said register with the address of data written to said main memory to determine if a tag bit is set indicating an overwrite of said first data block; and notifying said first cache of an overwrite.
Claim 20
Independent Claim
119 words
A system of maintaining coherency for a first data block transferred from a first memory to a second memory when a second data block is transferred to said first memory, wherein said first memory stores a plurality of data blocks, the method comprising: a register having addressable locations, each location corresponding to a data block in said first memory and each location having a one-to-one correspondence with a data block in said first memory, wherein a first of said locations has a tag bit; and means connected to said register and second memory for detecting an overwrite of said data block by examining the tag bit in said first location and for notifying said second memory of said overwrite.
Claim 21
Independent Claim
119 words
A system of maintaining coherency for a first data block transferred from a first memory to a second memory when a second data block is transferred to said first memory, wherein said first memory stores a plurality of data blocks, the method comprising: a register having addressable locations, each location corresponding to a data block in said first memory and each location having a one-to-one correspondence with a data block in said first memory, wherein a first of said locations has a tag bit; and means connected to said register and second memory for detecting an overwrite of said data block by examining the tag bit in said first location and for notifying said second memory of said overwrite.
Claim 22
Dependent Claim
28 words
The system of claim 16 wherein said detecting means includes: a signal line connected to said register for receiving address signals from data transfers to said first memory.
Claim 23
Dependent Claim
33 words
The system of claim 17 wherein said detecting means further includes: a state machine connected between said register and said second memory for receiving signals indicating whether said data block is being overwritten.
Claim 24
Dependent Claim
45 words
The system of claim 18 wherein said system further comprises a processor associated with said second memory means, and wherein said detecting means includes: a control line connecting said state machine to said processor for providing an interrupt signal when said data block is overwritten.
Claim 25
Dependent Claim
21 words
The system of claim 16 wherein said first memory is a main memory and said second memory is a cache memory.
Claim 26
Dependent Claim
31 words
The system of claim 16 further comprising: first and second busses; wherein said first memory is connected to both busses and said second memory is connected solely to said first bus.
Claim 27
Dependent Claim
32 words
The system of claim 21 further comprising: a third memory connected solely to said second bus; wherein each addressable location in said register has a bit corresponding to each of said busses.
Claim 28
Independent Claim
98 words
A system which detects when a first data element is overwritten by a second data element in a memory comprising: a tag register in the memory for storing a tag bit for the first data element, said register having addressable locations, each location corresponding to each data block in said memory and each location having a one-to-one correspondence with a data block in said memory; and control logic connected to the memory which examines the tag bit when the second data block is written to the memory and provides a signal that the first element has been overwritten.
Claim 29
Independent Claim
98 words
A system which detects when a first data element is overwritten by a second data element in a memory comprising: a tag register in the memory for storing a tag bit for the first data element, said register having addressable locations, each location corresponding to each data block in said memory and each location having a one-to-one correspondence with a data block in said memory; and control logic connected to the memory which examines the tag bit when the second data block is written to the memory and provides a signal that the first element has been overwritten.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-27 | 1997-03-29 | 1997-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-27 | 2001-03-29 | 2001-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-27 | 2005-03-29 | 2005-09-28 | $7700.00 | Window Closed / Lapsed |