US5802268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital processor with embedded eeprom memory
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-05-14
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Granted: 1998-09-01
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Expires: 2017-05-14
Abstract
Abstract There is disclosed an integrated circuit including a digital processor having EEPROM and a control register. The digital processor is capable of receiving data to be programmed into the EEPROM and is capable of programming the data into the EEPROM. The digital processor includes a control register for receiving bits to control a write line and an erase line. The digital processor also includes a processor core coupled to the control register by a data bus, the digital processor is coupled to the EEPROM by a ROM address bus and a RAM data bus. The EEPROM memory location identified by the ROM address bus is programmed to retain data latched onto the RAM data bus. This is achieved by the digital processor writing control bits to the control register to enable the write line for a write operation of sufficient duration to assure that the data on the RAM data bus is retained in the EEPROM memory address that is enabled.
Inventors
- 👤 Aaron Louis Fisher
- 👤 Alan Joel Greenberger
- 👤 Jay Patrick Wilshire
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:20
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/60; G06F8/65; G06F8/66; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1433
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
128 words
A method of programming memory locations of EEPROM on an integrated circuit in read-only memory space, the integrated circuit having a RAM, a RAM data bus, an address bus, and a digital processor with a core including a control register, the method comprising the steps of: reading data from the EEPROM to enable a particular word line at an address of a memory location that is to be programmed; latching the address into a register; writing data to RAM which causes data to be held on the RAM data bus; writing to a control register to enable an EEPROM write control; waiting a predetermined time period of sufficient duration to permit the write operation to be completed; and writing to a control register to disable the write control.
Claim 2
Independent Claim
128 words
A method of programming memory locations of EEPROM on an integrated circuit in read-only memory space, the integrated circuit having a RAM, a RAM data bus, an address bus, and a digital processor with a core including a control register, the method comprising the steps of: reading data from the EEPROM to enable a particular word line at an address of a memory location that is to be programmed; latching the address into a register; writing data to RAM which causes data to be held on the RAM data bus; writing to a control register to enable an EEPROM write control; waiting a predetermined time period of sufficient duration to permit the write operation to be completed; and writing to a control register to disable the write control.
Claim 3
Dependent Claim
37 words
The method of programming EEPROM as recited in claim 1, further comprising the step of: setting the duration of a timing loop to be of a sufficient length of time for a write operation to be completed.
Claim 4
Dependent Claim
26 words
The method of programming EEPROM as recited in claim 1, further comprising: storing the duration of time of a timing loop of a successful write operation.
Claim 5
Dependent Claim
54 words
The method of programming EEPROM as recited in claim 1, further comprising: reading the duration of time of a timing loop used in the last successful EEPROM programming operation; and setting the duration of a write operation timing loop to be the same duration as the duration of the last successful EEPROM programming operation.
Claim 6
Dependent Claim
22 words
The method of programming EEPROM as recited in claim 1, further comprising: verifying whether data has been successfully written to the EEPROM.
Claim 7
Dependent Claim
31 words
The method of programming EEPROM as recited in claim 5, further comprising: upon verifying that the writing operation was unsuccessful, increasing the duration of a writing loop by a predetermined increment.
Claim 8
Dependent Claim
33 words
The method of programming EEPROM as recited in claim 5, further comprising: upon verifying that the writing operation was unsuccessful increasing the voltage level used in the writing operation by a predetermined increment.
Claim 9
Dependent Claim
34 words
A method of programming an EEPROM as recited in claim 1, further comprising the step of: erasing the EEPROM memory locations prior to reading data from the EEPROM to enable a particular word line.
Claim 10
Dependent Claim
39 words
A method of programming an EEPROM as recited in claim 1, wherein the step of writing to a control register to enable an EEPROM write control, comprises: writing bits to the control register to activate a write control line.
Claim 11
Dependent Claim
40 words
A method of programming an EEPROM as recited in claim 1, wherein the step of writing data to RAM which causes data to be held on the RAM data bus comprises: latching a word of the program into a register.
Claim 12
Dependent Claim
26 words
A method of programming an EEPROM as recited in claim 1, wherein the step of waiting a predetermined amount of time comprises: entering a timing loop.
Claim 13
Dependent Claim
198 words
An integrated circuit having programmable memory in a read-only memory space, comprising: an EEPROM coupled to a ROM address bus and a data bus; a control register for receiving bits to control a write line and an erase line; a read address latch to latch the address of a memory location being read, so that a memory location at the same address may be subsequently written to; a digital processor including the EEPROM and the control register, the digital processor adapted to receive data transferred into the EEPROM and adapted to transfer the data into the EEPROM, the digital processor having a core coupled to the control register by a data bus to provide control bits thereto, the digital processor core coupled to the EEPROM by the ROM address bus and the data bus such that a memory location at an EEPROM address on the ROM address bus is latched into the read address latch upon being read and is programmed to retain data presented on the data bus by the digital processor writing control bits to a control register to cause a write line to make a predetermined logic state for the duration of a write operation.
Claim 14
Dependent Claim
198 words
An integrated circuit having programmable memory in a read-only memory space, comprising: an EEPROM coupled to a ROM address bus and a data bus; a control register for receiving bits to control a write line and an erase line; a read address latch to latch the address of a memory location being read, so that a memory location at the same address may be subsequently written to; a digital processor including the EEPROM and the control register, the digital processor adapted to receive data transferred into the EEPROM and adapted to transfer the data into the EEPROM, the digital processor having a core coupled to the control register by a data bus to provide control bits thereto, the digital processor core coupled to the EEPROM by the ROM address bus and the data bus such that a memory location at an EEPROM address on the ROM address bus is latched into the read address latch upon being read and is programmed to retain data presented on the data bus by the digital processor writing control bits to a control register to cause a write line to make a predetermined logic state for the duration of a write operation.
Claim 15
Independent Claim
82 words
A method of programming programmable read only memory on an integrated circuit in read-only memory space, the integrated circuit having a digital processor, comprising the steps of: reading the content of a memory location; latching an address of the memory location into a register; writing data on a data bus; enabling a programmable read only memory write line; and transferring the data from the data bus to the memory location of the latched address of programmable read-only memory in read-only memory space.
Claim 16
Independent Claim
82 words
A method of programming programmable read only memory on an integrated circuit in read-only memory space, the integrated circuit having a digital processor, comprising the steps of: reading the content of a memory location; latching an address of the memory location into a register; writing data on a data bus; enabling a programmable read only memory write line; and transferring the data from the data bus to the memory location of the latched address of programmable read-only memory in read-only memory space.
Claim 17
Dependent Claim
20 words
The method of claim 13, further comprising the step of downloading the data through a port to the digital processor.
Claim 18
Dependent Claim
32 words
The method of claim 13, further comprising the step of setting a write operation timing loop duration to be of a sufficient length of time for a write operation to be completed.
Claim 19
Dependent Claim
24 words
The method of claim 15, further comprising the step of storing a duration of time of a timing loop of a successful write operation.
Claim 20
Dependent Claim
49 words
The method of claim 15, further comprising the steps of: reading a duration of time of a timing loop used in a successful write operation; and setting the duration of a write operation timing loop to be the same duration as the duration of the last successful write operation.
Claim 21
Dependent Claim
20 words
The method of claim 13, further comprising: verifying whether data has been successfully written to the programmable read only memory.
Claim 22
Dependent Claim
26 words
The method of claim 18, further comprising: upon verifying that the write operation was unsuccessful, increasing the duration of a write loop by a predetermined increment.
Claim 23
Dependent Claim
28 words
The method of claim 18, further comprising: upon verifying that the writing operation was unsuccessful increasing the voltage level used in the writing operation by a predetermined increment.
Claim 24
Dependent Claim
30 words
The method of claim 13, further comprising the step of: erasing the memory locations prior to reading data from the programmable read only memory to enable a particular word line.
Claim 25
Independent Claim
92 words
A method of programming programmable read-only memory in read-only memory space of a digital processor, comprising the steps of: reading from memory space at an address to place an address on a read-only memory address bus: latching the address into a register; writing on a random access memory data bus to the latched address to make data available to programmable memory in read-only memory space; enabling a programmable memory write line; and transferring data from the data bus to the memory location of the latched address of programmable memory in read-only memory.
Claim 26
Independent Claim
92 words
A method of programming programmable read-only memory in read-only memory space of a digital processor, comprising the steps of: reading from memory space at an address to place an address on a read-only memory address bus: latching the address into a register; writing on a random access memory data bus to the latched address to make data available to programmable memory in read-only memory space; enabling a programmable memory write line; and transferring data from the data bus to the memory location of the latched address of programmable memory in read-only memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |