US5187683A
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Method for programming EEPROM memory arrays
Assignee: Texas Instruments Inc
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Filing: 1990-08-31
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Granted: 1993-02-16
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Expires: 2010-08-31
Abstract
Abstract A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline. After a pre-charge time interval, the fifth programming voltage is applied to each same-type deselected column line and, after an optional additional pre-charge time interval, the second programming voltage is applied to the selected wordline. After a program time interval, the third programming voltage is applied to the selected wordline and, after an optional discharge time interval, the first programming voltage is applied to each same-type deselected column line. Each deselected wordline is maintained at the fourth programming voltage for an additional discharge time interval. The third, fourth and fifth programming voltages may have the same value.
Inventors
- 👤 Manzur Gill
- 👤 Sung-Wei Lin
- 👤 Sebastiano D'Arrigo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:34
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/10
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
206 words
A method for programming a selected memory cell in a semiconductor array of deselected cells and of said selected cell, said selected cell connected to at least a selected column line and a selected worline, each said deselected memory cell in said array connected to at least a deselected column line or a deselected wordline, said method comprising: preselecting first, second, third, fourth and fifth programming voltages such that said second programming voltage is more positive than said first programming voltage and such that said third, fourth and fifth programming voltages are intermediate between said first and second programming voltages; with said first programming voltage applied at least to said selected column line and each said deselected column line, applying said third programming voltage to said selected wordline and said fourth programming voltage to each said deselected wordline; after a pre-charge time interval, applying said fifth programming voltage to each said deselected column line and applying said second programming voltage to said selected wordline; after a program time interval, applying said third programming voltage to said selected wordline and applying said first programming voltage to each said deselected column line; and maintaining each said deselected wordline at said fourth programming voltage for a discharge time interval.
Claim 2
Independent Claim
206 words
A method for programming a selected memory cell in a semiconductor array of deselected cells and of said selected cell, said selected cell connected to at least a selected column line and a selected worline, each said deselected memory cell in said array connected to at least a deselected column line or a deselected wordline, said method comprising: preselecting first, second, third, fourth and fifth programming voltages such that said second programming voltage is more positive than said first programming voltage and such that said third, fourth and fifth programming voltages are intermediate between said first and second programming voltages; with said first programming voltage applied at least to said selected column line and each said deselected column line, applying said third programming voltage to said selected wordline and said fourth programming voltage to each said deselected wordline; after a pre-charge time interval, applying said fifth programming voltage to each said deselected column line and applying said second programming voltage to said selected wordline; after a program time interval, applying said third programming voltage to said selected wordline and applying said first programming voltage to each said deselected column line; and maintaining each said deselected wordline at said fourth programming voltage for a discharge time interval.
Claim 3
Dependent Claim
41 words
The method of claim 1, wherein, after said pre-charge time interval and after said fifth programming voltage is applied to each said deselected column line, said second programming voltage is applied to said selected wordline after a second pre-charge time interval.
Claim 4
Dependent Claim
39 words
The method of claim 1, wherein, after said program time interval and after applying said third programming voltage to said selected wordline, said first programming voltage is applied to each said deselected column line after an optional time interval.
Claim 5
Dependent Claim
48 words
The method of claim 1, wherein, after said pre-charge time interval, said fifth programming voltage is applied to each said deselected column line to prevent programming of said selected cell and wherein, after said program time interval, said first programming voltage is applied to said selected column line.
Claim 6
Dependent Claim
16 words
The method of claim 1, wherein said third and fourth programming voltages have the same value.
Claim 7
Dependent Claim
16 words
The method of claim 1, wherein said fourth and fifth programming voltages have the same value.
Claim 8
Dependent Claim
15 words
The method of claim 1, wherein said third and fifth voltages have the same value.
Claim 9
Dependent Claim
76 words
The method of claim 1, wherein said selected memory cell has a floating gate capacitively coupled to said selected column line and to said selected wordline and wherein said step of preselecting said first and second programming voltages comprises: selecting said first programming voltage to be approximately 0 volts; and selecting said second programming voltage to be at a positive potential sufficient to cause electrons to flow from said selected column line to said floating gate.
Claim 10
Dependent Claim
60 words
The method of claim 1, wherein said selected memory cell has a floating gate capacitively coupled to said selected column line and to said selected wordline and wherein said step of preselecting said first and second programming voltages comprises: selecting said first programming voltage to be approximately 0 volts; and selecting said second programming voltage to be approximately +18 volts.
Claim 11
Dependent Claim
14 words
The method of claim 1, wherein said third programming voltage is approximately 5 volts.
Claim 12
Dependent Claim
20 words
The method of claim 1, wherein said fourth programming voltage is in the approximate range of 7 to 10 volts.
Claim 13
Dependent Claim
20 words
The method of claim 1, wherein said fifth programming voltage is in the approximate range of 6 to 7 volts.
Claim 14
Independent Claim
218 words
A method for preventing unintentional deprogramming of a deselected nonvolatile memory cell in an array of deselected cells and of a selected cell while programming said selected memory cell in said array, each said deselected memory cell in said array connected to at least a deselected column line or a deselected wordline, said selected cell connected to at least a selected column line and a selected wordline, said method comprising: preselecting first, second, third, fourth and fifth programming voltages such that said second programming voltage is more positive than said first programming voltage and such that said third, fourth and fifth programming voltages are intermediate between said first and second programming voltages; with said first programming voltage applied at least to said selected column line and each said deselected column line, applying said third programming voltage to said selected wordline and said fourth programming voltage to each said deselected wordline; after a pre-charge time interval, applying said fifth programming voltage to each said deselected column line and applying said second programming voltage to said selected wordline; after a program time interval, applying said third programming voltage to said selected wordline and applying said first programming voltage to each said deselected column line; and maintaining each said deselected wordline at said fourth programming voltage for a discharge time interval.
Claim 15
Independent Claim
218 words
A method for preventing unintentional deprogramming of a deselected nonvolatile memory cell in an array of deselected cells and of a selected cell while programming said selected memory cell in said array, each said deselected memory cell in said array connected to at least a deselected column line or a deselected wordline, said selected cell connected to at least a selected column line and a selected wordline, said method comprising: preselecting first, second, third, fourth and fifth programming voltages such that said second programming voltage is more positive than said first programming voltage and such that said third, fourth and fifth programming voltages are intermediate between said first and second programming voltages; with said first programming voltage applied at least to said selected column line and each said deselected column line, applying said third programming voltage to said selected wordline and said fourth programming voltage to each said deselected wordline; after a pre-charge time interval, applying said fifth programming voltage to each said deselected column line and applying said second programming voltage to said selected wordline; after a program time interval, applying said third programming voltage to said selected wordline and applying said first programming voltage to each said deselected column line; and maintaining each said deselected wordline at said fourth programming voltage for a discharge time interval.
Claim 16
Dependent Claim
41 words
The method of claim 13, wherein, after said pre-charge time interval and after said fifth programming voltage is applied to each said deselected column line, said second programming voltage is applied to said selected wordline after a second pre-charge time interval.
Claim 17
Dependent Claim
39 words
The method of claim 13, wherein, after said program time interval and after applying said third programming voltage to said selected wordline, said first programming voltage is applied to each said deselected column line after an optional time interval.
Claim 18
Dependent Claim
48 words
The method of claim 13, wherein, after said pre-charge time interval, said fifth programming voltage is applied to each said deselected column line to prevent programming of said selected cell and wherein, after said program time interval, said first programming voltage is applied to said selected column line.
Claim 19
Dependent Claim
16 words
The method of claim 13, wherein said third and fourth programming voltages have the same value.
Claim 20
Dependent Claim
16 words
The method of claim 13, wherein said fourth and fifth programming voltages have the same value.
Claim 21
Dependent Claim
15 words
The method of claim 13, wherein said third and fifth voltages have the same value.
Claim 22
Dependent Claim
76 words
The method of claim 13, wherein said selected memory cell has a floating gate capacitively coupled to said selected column line and to said selected wordline and wherein said step of preselecting said first and second programming voltages comprises: selecting said first programming voltage to be approximately 0 volts; and selecting said second programming voltage to be at a positive potential sufficient to cause electrons to flow from said selected column line to said floating gate.
Claim 23
Dependent Claim
60 words
The method of claim 13, wherein said selected memory cell has a floating gate capacitively coupled to said selected column line and to said selected wordline and wherein said step of preselecting said first and second programming voltages comprises: selecting said first programming voltage to be approximately 0 volts; and selecting said second programming voltage to be approximately +18 volts.
Claim 24
Dependent Claim
14 words
The method of claim 13, wherein said third programming voltage is approximately 5 volts.
Claim 25
Dependent Claim
20 words
The method of claim 13, wherein said fourth programming voltage is in the approximate range of 7 to 10 volts.
Claim 26
Dependent Claim
20 words
The method of claim 13, wherein said fifth programming voltage is in the approximate range of 6 to 7 volts.
References Cited (Backward Citations)
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