Patent US5801960A successfully refreshed from Google Patents.
US5801960A
Expired / Lapsed
US
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Layout method of wiring pattern for semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1997-11-03
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Granted: 1998-09-01
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Expires: 2017-11-03
Abstract
Abstract A layout method of designing a wiring pattern on a semiconductor integrated circuit chip according to the present invention comprises three steps of omitting a part of or all of a wiring pattern within cells for a plurality of circuit elements for layout results of these predetermined circuit elements to prepare wiring obstruction data (step 1); deciding a specific wiring path connecting between the cells with reference to the prepared wiring obstruction data (step 2); and repositioning of the cell to correct the layout with no design rule violation and no short between this specific wiring path and the wiring pattern within cells (step 3). The pattern layout is performed so that the specific wiring path is wired in the shortest length of wiring path without making a snaking wire path and also uncomplete wiring does not happen to occur.
Inventors
- 👤 Midori Takano
- 👤 Fumihiro Minami
- 👤 Mutsunori Igarashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:07
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/394
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
217 words
A layout method of a circuit pattern for a semiconductor integrated circuit (IC), comprising the steps of: (a) a first step of laying out cells by tentatively placing a plurality of movable cells and permanently fixing a plurality of immovable cells, in predetermined positions, each movable and immovable cell having an internal wiring pattern for forming a circuit element, respectively; (b) a second step of preparing wiring obstruction data for searching a wiring path for a specific signal with respect to the cell layout results of said first step, comprising including in the obstruction data the internal wiring patterns of said immovable cells and including only a portion or none of the internal wiring patterns of said movable cells; (c) a third step of searching and fixing the wiring path for the specific signal with reference to the prepared wiring obstruction data so as to avoid design rule violations in said immovable cells while enabling the wiring path to pass through said immovable and movable cells; (d) a fourth step of removing any short circuit between said wiring path and said internal wiring pattern in one or more of said movable cells or removing design rule violations by repositioning corresponding ones of said movable cells; and (e) a fifth step of deciding wiring paths of remaining signals.
Claim 2
Dependent Claim
217 words
A layout method of a circuit pattern for a semiconductor integrated circuit (IC), comprising the steps of: (a) a first step of laying out cells by tentatively placing a plurality of movable cells and permanently fixing a plurality of immovable cells, in predetermined positions, each movable and immovable cell having an internal wiring pattern for forming a circuit element, respectively; (b) a second step of preparing wiring obstruction data for searching a wiring path for a specific signal with respect to the cell layout results of said first step, comprising including in the obstruction data the internal wiring patterns of said immovable cells and including only a portion or none of the internal wiring patterns of said movable cells; (c) a third step of searching and fixing the wiring path for the specific signal with reference to the prepared wiring obstruction data so as to avoid design rule violations in said immovable cells while enabling the wiring path to pass through said immovable and movable cells; (d) a fourth step of removing any short circuit between said wiring path and said internal wiring pattern in one or more of said movable cells or removing design rule violations by repositioning corresponding ones of said movable cells; and (e) a fifth step of deciding wiring paths of remaining signals.
Claim 3
Dependent Claim
36 words
A layout method as claimed in claim 1, wherein in said second step, all of the internal wiring patterns within said movable cells laid out in said first step are omitted to prepare said-wiring obstruction data.
Claim 4
Dependent Claim
50 words
A layout method as claimed in claim 1, wherein the wiring path for said specific signal is one for a signal whose electric characteristics should be taken into consideration, and the number of snaking portions in the wiring path for the specific signal decided in said third step are minimized.
Claim 5
Dependent Claim
51 words
A layout method as claimed in claim 1, wherein in said second step, at least a part of the internal wiring patterns of said movable cells which are not connected to the wiring path for the specific signal, and which can be repositioned are omitted to prepare the wiring obstruction data.
Claim 6
Dependent Claim
126 words
A layout method as claimed in claim 1, wherein said fourth step, comprises: a repositioning of a first movable cell which has a design rule violation or a short circuit between the internal wiring pattern in said first movable cell and the wiring path for the specific signal by a minimum distance in a direction capable of removing the design rule violation or the short circuit and a repositioning of a second movable cell by a minimum distance in a direction capable of removing an overlapping between the first and second movable cells so that a new design rule violation or a new short circuit between the internal wiring pattern in the second movable cell and the wiring path for the specific signal is not caused.
Claim 7
Dependent Claim
31 words
A layout method as claimed in claim 4, wherein the internal wiring patterns in the first and second movable cells are not connected with the wiring path for the specific signal.
Claim 8
Dependent Claim
125 words
A layout method as claimed in claim 2, wherein said fourth step comprises: a repositioning of a first movable cell having a design rule violation or a short circuit between the internal wiring pattern in the first movable cell and the wiring path for the specific signal by a minimum distance in a direction capable of removing the design rule violation or the short circuit; and a repositioning of a second movable cell by a minimum distance in a direction capable of removing an overlapping between the first and second movable cells so that a new design rule violation or a new short circuit between the internal wiring pattern in the second movable cell and the wiring path for the specific signal is not caused.
Claim 9
Dependent Claim
125 words
A layout method as claimed in claim 3, wherein said fourth step comprises: a repositioning of a first movable cell having a design rule violation or a short circuit between the internal wiring pattern in the first movable cell and the wiring path for the specific signal by a minimum distance in a direction capable of removing the design rule violation or the short circuit; and a repositioning of a second movable cell by a minimum distance in a direction capable of removing an overlapping between the first and second movable cells so that a new design rule violation or a new short circuit between the internal wiring pattern in the second movable cell and the wiring path for the specific signal is not caused.
Claim 10
Dependent Claim
125 words
A layout method as claimed in claims 4, wherein said fourth step comprises: a repositioning of a first movable cell having a design rule violation or a short circuit between the internal wiring pattern in the first movable cell and the wiring path for the specific signal by a minimum distance in a direction capable of removing the design rule violation or the short circuit; and a repositioning of a second movable cell by a minimum distance in a direction capable of removing an overlapping between the first and second movable cells so that a new design rule violation or a new short circuit between the internal wiring pattern in the second movable cell and the wiring path for the specific signal is not caused.
Claim 11
Dependent Claim
27 words
A layout method as claimed in claim 9, wherein the internal wiring patterns in the first and second movable cells are not connected with the specific signal.
Claim 12
Dependent Claim
45 words
A layout method as claimed in claim 1, wherein said semiconductor integrated circuit has a first metal layer, and a second metal layer disposed over the first metal layer, and said wiring path for the specific signal comprises wiring formed in the second metal layer.
Claim 13
Dependent Claim
22 words
A layout method as claimed in claim 11, wherein said internal wiring patterns are formed at least in the first metal layer.
Claim 14
Dependent Claim
21 words
A layout method as claimed in claim 12, wherein said internal wiring patterns are formed partially in the second metal layer.
Claim 15
Dependent Claim
38 words
A layout method as claimed in claim 1, wherein said wiring obstruction data comprises: the internal wiring patterns in said immovable cells; and the internal wiring patterns to be wired to said wiring path for the specific signal.
Claim 16
Dependent Claim
22 words
A layout method as claimed in claim 14, wherein said wiring obstruction data further comprises an already wired pattern for connecting cells.
Claim 17
Dependent Claim
24 words
A layout method as claimed in claim 13, wherein said wiring obstruction data is limited to wiring patterns formed as the first metal layer.
Claim 18
Dependent Claim
56 words
A layout method as claimed in claim 13, wherein a dummy internal wiring pattern is additionally prepared as the second metal layer and is included as the wiring obstruction data to ensure a wiring lead-out, the dummy internal wiring pattern being removed after said fourth step so as not to exist as a real circuit pattern.
Claim 19
Dependent Claim
41 words
A layout method as claimed in claim 17, wherein said dummy internal wiring pattern has a same rectangular shape as a terminal rectangle on the first metal layer having a shorter side length than a predetermined value in a specific direction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |