Charge sharing detection circuit for anti-fuses

Claim 2

A detection circuit for detecting first and second conditions for a programmable logic device, said detection circuit comprising: a detection node; a precharge circuit for applying a precharge voltage to the programmable logic device during a precharge time interval; and a circuit for coupling the programmable logic device to said detection node after a predetermined discharge time interval after said precharge time interval to provide a voltage at said detection node that is indicative of the ability of the programmable logic device to retain a charge for the duration of said predetermined discharge time interval.

Claim 3

The detection circuit according to claim 1, and further including an output circuit coupled to said detection node, said output circuit being responsive to the voltage existing at said detection node after the end of said predetermined discharge time interval to provide a first output for indicating a first condition for the programmable logic device and a second output for indicating a second condition for the programmable logic device.

Claim 4

A detection circuit for detecting the condition of an anti-fuse, said detection circuit comprising: a detection node; a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval; a coupling circuit for coupling the anti-fuse to said detection node after a predetermined discharge interval after said precharge time interval to provide a voltage at said detection node that is indicative of the charge remaining on said anti-fuse after the end of said predetermined discharge interval; and an output circuit coupled to said detection node, said output circuit being responsive to the voltage existing at said detection node to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.

Claim 5

A detection circuit for detecting the condition of an anti-fuse, said detection circuit comprising: a detection node; a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval; a coupling circuit for coupling the anti-fuse to said detection node after a predetermined discharge interval after said precharge time interval to provide a voltage at said detection node that is indicative of the charge remaining on said anti-fuse after the end of said predetermined discharge interval; and an output circuit coupled to said detection node, said output circuit being responsive to the voltage existing at said detection node to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.

Claim 6

The detection circuit according to claim 3, wherein said coupling circuit includes a switching device for isolating the anti-fuse from said detection node during said precharge time interval.

Claim 7

The detection circuit according to claim 4, wherein said switching device comprises a first transistor interposed between said detection node and the anti-fuse, said first transistor having a control input connected to receive an enabling signal for operating said first transistor between a first state in which said first transistor isolates the anti-fuse from said detection node and a second state in which said first transistor couples the anti-fuse to said detection node.

Claim 8

The detection circuit according to claim 5, and further including a second transistor interposed between said detection node and a first voltage supply, said second transistor having an input connected to receive an enabling signal for operating said second transistor between a first state in which said second transistor permits said detection node to be coupled to said first voltage supply, and a second state in which said second transistor prevents said detection node from being coupled to said first voltage supply.

Claim 9

A detection circuit for detecting unblown and blown conditions for an anti-fuse, said detection circuit comprising: a detection node; a first switching device for coupling said detection node to a first voltage supply; a second switching device interposed between the anti-fuse and said detection node; and a precharge circuit for applying a precharge voltage to the anti-fuse for charging the anti-fuse during a precharge time interval; said first switching device being responsive to an enabling signal to isolate said detection node from the first voltage supply, said second switching device being responsive to said enabling signal to couple the anti-fuse to said detection node at the end of a discharge time interval initiated at the end of the precharge time interval, and while said detection node is isolated from the first voltage supply by said first switching device, for providing at said detection node a voltage the magnitude of which is dependent upon the charge remaining on said anti-fuse after the end of said discharge time interval, and is thus indicative of the condition of the anti-fuse.

Claim 10

A detection circuit for detecting unblown and blown conditions for an anti-fuse, said detection circuit comprising: a detection node; a first switching device for coupling said detection node to a first voltage supply; a second switching device interposed between the anti-fuse and said detection node; and a precharge circuit for applying a precharge voltage to the anti-fuse for charging the anti-fuse during a precharge time interval; said first switching device being responsive to an enabling signal to isolate said detection node from the first voltage supply, said second switching device being responsive to said enabling signal to couple the anti-fuse to said detection node at the end of a discharge time interval initiated at the end of the precharge time interval, and while said detection node is isolated from the first voltage supply by said first switching device, for providing at said detection node a voltage the magnitude of which is dependent upon the charge remaining on said anti-fuse after the end of said discharge time interval, and is thus indicative of the condition of the anti-fuse.

Claim 11

The detection circuit according to claim 7, and further comprising an output circuit coupled to said detection node, said output circuit being responsive to the voltage existing at said detection node after the end of said discharge time interval for providing a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.

Claim 12

The detection circuit according to claim 8, and further including a third switching device which is connected in series with said first switching device between said detection node and said first voltage supply, said third switching device having a control input connected to said output circuit for receiving a feedback disable signal, said feedback disable signal causing said third switching device to isolate said detection node from said first voltage supply for one of the conditions of the anti-fuse.

Claim 13

The detection circuit according to claim 9, wherein said first switching device comprises a first p-channel transistor having a gate coupled to an input node of the detection circuit for receiving said enabling signal, wherein said third switching device comprises a second p-channel transistor having a gate coupled to said output circuit for receiving said feedback disable signal, and wherein said second switching device is an n-channel transistor having a gate coupled to said input node for receiving said enabling signal.

Claim 14

The detection circuit according to claim 9, wherein said output circuit comprises a first inverter circuit having an input connected to said detection node and an output connected to an intermediate node, and a second inverter circuit having an input connected to said intermediate node and an output connected to an output node.

Claim 15

A semiconductor memory device, comprising: a memory array having a plurality of addressable memory cells; an address decoder circuit responsive to address signals for accessing memory cells; a programmable array associated with said address decoder circuit, said programmable array including at least one anti-fuse and at least one detection circuit for detecting first and second conditions for an anti-fuse, said detection circuit comprising: a detection node; a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval; a coupling circuit for coupling the anti-fuse to said detection node after a predetermined discharge time interval after said precharge time interval to provide a voltage at said detection node that is indicative of the ability of the anti-fuse to retain a charge for the duration of said predetermined discharge time interval; and an output circuit coupled to said detection node, said output circuit being responsive to the voltage existing at said detection node after the end of said predetermined discharge time interval to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.

Claim 16

A semiconductor memory device, comprising: a memory array having a plurality of addressable memory cells; an address decoder circuit responsive to address signals for accessing memory cells; a programmable array associated with said address decoder circuit, said programmable array including at least one anti-fuse and at least one detection circuit for detecting first and second conditions for an anti-fuse, said detection circuit comprising: a detection node; a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval; a coupling circuit for coupling the anti-fuse to said detection node after a predetermined discharge time interval after said precharge time interval to provide a voltage at said detection node that is indicative of the ability of the anti-fuse to retain a charge for the duration of said predetermined discharge time interval; and an output circuit coupled to said detection node, said output circuit being responsive to the voltage existing at said detection node after the end of said predetermined discharge time interval to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.

Claim 17

The semiconductor memory device according to claim 12, wherein said coupling circuit includes a switching device for isolating the anti-fuse from said detection node during the precharge time interval.

Claim 20

The method according to claim 14, and including isolating the anti-fuse from said detection node during the precharge time interval.

Claim 23

The method according to claim 16, wherein precharging the anti-fuse includes applying a precharge voltage to the anti-fuse for charging the anti-fuse; and terminating the application of the precharge voltage to the anti-fuse prior to coupling the anti-fuse to said detection node.