US5801566A
Expired / Lapsed
US
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System clock generating circuit for a semiconductor device
Assignee: Renesas Design Corp
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Filing: 1996-08-05
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Granted: 1998-09-01
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Expires: 2016-08-05
Abstract
Abstract According to the present invention, when a semiconductor device is tested, a signal for test can be set in the semiconductor device at a desired timing. A second delay circuit of the present invention has the same structure as a first delay circuit in a phase lock loop, and receives a control voltage from the phase lock loop so as to generate a clock signal with a frequency according to the control voltage and to delay and output the clock signal. A second pulse generator generates two-phase clocks by using delayed signals generated by the second delay circuit. Switches are used for switching between a system clock output terminal during an actually active time and a system clock output terminal during testing.
Inventors
- 👤 Nobuhiko Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:17
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K; H03K5/00; H03K5/13; H03K5/133; H03L7/081; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/099; H03L7/0995
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
312 words
A system clock generating circuit for generating two-phase clock signals and preventing high periods of the two-phase clock signals from overlapping, the circuit comprising: a phase lock loop including: a first delay circuit for generating a first clock signal with a frequency according to a control voltage depending upon a phase difference between a reference clock signal and a feedback clock signal and for delaying and outputting the first clock signal, a first pulse generator coupled to the first delay circuit for generating first and second two-phase clock signals and preventing high periods of the first and second two-phase clock signals from overlapping, in response to the first clock signal delayed by the first delay circuit; a second delay circuit structurally similar to the first delay circuit and receiving the control voltage, for generating a second clock signal with a frequency according to the control voltage and for delaying and outputting the second clock signal; a second pulse generator coupled to the second delay circuit for generating third and fourth two-phase clock signals and preventing high periods of the third and fourth two-phase clock signals from overlapping, in response to the second clock signal delayed by the second delay circuit; first switching means for switching between a first state in which a first input clock signal is fed to the phase lock loop and the second delay circuit is open-circuited and a second state in which a second input clock signal is fed to the phase lock loop and a third input clock signal is fed to the second delay circuit; and second switching means for selecting at least one of: (a) the first and second two-phase clock signals generated by the first pulse generator and (b) the third and fourth two-phase clock signals generated by the second pulse generator and for outputting the selected two-phase clock signals as system clock signals.
Claim 2
Independent Claim
312 words
A system clock generating circuit for generating two-phase clock signals and preventing high periods of the two-phase clock signals from overlapping, the circuit comprising: a phase lock loop including: a first delay circuit for generating a first clock signal with a frequency according to a control voltage depending upon a phase difference between a reference clock signal and a feedback clock signal and for delaying and outputting the first clock signal, a first pulse generator coupled to the first delay circuit for generating first and second two-phase clock signals and preventing high periods of the first and second two-phase clock signals from overlapping, in response to the first clock signal delayed by the first delay circuit; a second delay circuit structurally similar to the first delay circuit and receiving the control voltage, for generating a second clock signal with a frequency according to the control voltage and for delaying and outputting the second clock signal; a second pulse generator coupled to the second delay circuit for generating third and fourth two-phase clock signals and preventing high periods of the third and fourth two-phase clock signals from overlapping, in response to the second clock signal delayed by the second delay circuit; first switching means for switching between a first state in which a first input clock signal is fed to the phase lock loop and the second delay circuit is open-circuited and a second state in which a second input clock signal is fed to the phase lock loop and a third input clock signal is fed to the second delay circuit; and second switching means for selecting at least one of: (a) the first and second two-phase clock signals generated by the first pulse generator and (b) the third and fourth two-phase clock signals generated by the second pulse generator and for outputting the selected two-phase clock signals as system clock signals.
Claim 3
Dependent Claim
51 words
The system clock generating circuit according to claim 1 wherein the first switching means includes a first switch arranged between a clock input terminal and a reference clock signal input terminal of the phase lock loop, and `a second switch arranged between the clock input terminal and the second delay circuit.
Claim 4
Independent Claim
213 words
A system clock generating circuit for generating two-phase clock signals and preventing high periods of the two-phase clock signals from overlapping, the circuit comprising: phase lock loop including: a first delay circuit for generating a first clock signal with a frequency according to a control voltage depending upon a phase difference between a reference clock signal and a feedback clock signal and for delaying and outputting the first clock signal; a second delay circuit structurally similar to the first delay circuit and receiving the control voltage, for generating a second clock signal with a frequency according to the control voltage and for delaying and outputting the second clock signal; a pulse generator coupled to the second delay circuit for generating first and second two-phase clock signals and preventing high periods of the first and second two-phase clock signals from overlapping, in response to the second clock signal delayed by the second delay circuit; and switching means for switching between a first state in which a first input clock signal is fed to the phase lock loop and to the second delay circuit and a second state in which a second input clock signal is fed to the phase lock loop and the first input clock signal is fed to the second delay circuit.
Claim 5
Independent Claim
213 words
A system clock generating circuit for generating two-phase clock signals and preventing high periods of the two-phase clock signals from overlapping, the circuit comprising: phase lock loop including: a first delay circuit for generating a first clock signal with a frequency according to a control voltage depending upon a phase difference between a reference clock signal and a feedback clock signal and for delaying and outputting the first clock signal; a second delay circuit structurally similar to the first delay circuit and receiving the control voltage, for generating a second clock signal with a frequency according to the control voltage and for delaying and outputting the second clock signal; a pulse generator coupled to the second delay circuit for generating first and second two-phase clock signals and preventing high periods of the first and second two-phase clock signals from overlapping, in response to the second clock signal delayed by the second delay circuit; and switching means for switching between a first state in which a first input clock signal is fed to the phase lock loop and to the second delay circuit and a second state in which a second input clock signal is fed to the phase lock loop and the first input clock signal is fed to the second delay circuit.
Claim 6
Dependent Claim
35 words
The system clock generating circuit according to claim 3, wherein the switching means includes a first switch arranged between a clock input terminal and a reference clock signal input terminal of the phase lock loop.
Claim 7
Dependent Claim
20 words
The system clock generating circuit of claim 1 wherein the first, second, and third input clock signals have identical frequencies.
Claim 8
Dependent Claim
26 words
The system clock generating circuit of claim 1 wherein, during testing, the third input clock signal has a lower frequency than the second input clock signal.
Claim 9
Dependent Claim
19 words
The system clock generating circuit of claim 3 wherein the first and second input clock signals have identical frequencies.
Claim 10
Dependent Claim
26 words
The system clock generating circuit of claim 3 wherein, during testing, the first input clock signal has a lower frequency than the second input clock signal.
References Cited (Backward Citations)
US4494021A
Cited
US5039893A
Cited
JPH0289422A
Cited
US5428309A
Cited
US5081428A
Cited
US5146121A
Cited
US5475344A
Cited
US5638019A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |