Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
103 words
A system for generating a skewed clock signal, comprising: means for creating a feedback oscillation signal using a first controllable delay line; a second controllable delay line, fabricated to have substantially identical functional characteristics to the first controllable delay line, connected to receive a base clock signal; frequency comparator means for concurrently controlling delay in the first and second controllable delay lines in proportion to the difference between the frequency of the feedback oscillation signal and a subharmonic of the base clock signal; and means for tapping the base clock signal as skewed at an incremental position along the second controllable delay line.
Claim 2
Independent Claim
103 words
A system for generating a skewed clock signal, comprising: means for creating a feedback oscillation signal using a first controllable delay line; a second controllable delay line, fabricated to have substantially identical functional characteristics to the first controllable delay line, connected to receive a base clock signal; frequency comparator means for concurrently controlling delay in the first and second controllable delay lines in proportion to the difference between the frequency of the feedback oscillation signal and a subharmonic of the base clock signal; and means for tapping the base clock signal as skewed at an incremental position along the second controllable delay line.
Claim 3
Dependent Claim
23 words
The system recited in claim 1, wherein the frequency of the feedback oscillation signal is half the frequency of the base clock signal.
Claim 4
Dependent Claim
29 words
The system recited in claim 2, wherein the frequency comparator compares the feedback oscillation signal with the output of a frequency divider directly driven by the base clock signal.
Claim 5
Dependent Claim
36 words
The system recited in claim 2, wherein the means for tapping the base clock signal comprises at least one physical connection to a node between stages of multiple transistorized delay elements in the second delay line.
Claim 6
Independent Claim
103 words
A method for generating a skewed clock signal, comprising the steps of: creating a feedback oscillation signal using a first controllable delay line; providing a base clock signal to a second controllable delay line, the second controllable delay line being fabricated to have substantially identical functional characteristics to the first controllable delay line; concurrently controlling delay in the first and second controllable delay lines in proportion to the difference between the frequency of the feedback oscillation signal and a subharmonic of the base clock signal; and tapping the base clock signal as skewed at an incremental position along the second controllable delay line.
Claim 7
Independent Claim
103 words
A method for generating a skewed clock signal, comprising the steps of: creating a feedback oscillation signal using a first controllable delay line; providing a base clock signal to a second controllable delay line, the second controllable delay line being fabricated to have substantially identical functional characteristics to the first controllable delay line; concurrently controlling delay in the first and second controllable delay lines in proportion to the difference between the frequency of the feedback oscillation signal and a subharmonic of the base clock signal; and tapping the base clock signal as skewed at an incremental position along the second controllable delay line.
Claim 8
Dependent Claim
23 words
The method recited in claim 5, wherein the frequency of the feedback oscillation signal is half the frequency of the base clock signal.
Claim 9
Dependent Claim
33 words
The method recited in claim 6, wherein the concurrent control step is accomplished by comparing the feedback oscillation signal with the output of a frequency divider directly driven by the base clock signal.
Claim 10
Dependent Claim
29 words
The method recited in claim 6, wherein the tapping step is accomplished by connecting to a node between stages of multiple transistorized delay elements in the second delay line.