US5798971A
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US
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Nonvolatile memory with output mode configuration
Assignee: Intel Corp
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Filing: 1997-01-28
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Granted: 1998-08-25
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Expires: 2017-01-28
Abstract
Abstract A nonvolatile memory includes a memory array and a buffer circuit for applying data read from the memory array to external circuitry. A compensation circuit is coupled to the buffer circuit for providing output compensation to the buffer circuit when enabled. The buffer circuit has (1) a first output speed when the compensation circuit is enabled and (2) a second output speed when the compensation circuit is disabled. A configuration circuit is coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured between the first and second output speeds. A method of configuring a nonvolatile memory between a first output speed and a second output speed is also described.
Inventors
- 👤 Robert E. Larsen
- 👤 Richard J. Durante
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:18
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1069
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
110 words
A nonvolatile memory, comprising: (A) a memory array; (B) a buffer circuit for applying data read from the memory array to external circuitry; (C) a compensation circuit coupled to the buffer circuit form providing programmable output compensation to the buffer circuit when enabled, wherein the buffer circuit has (1) a first prespecified output speed when the compensation circuit is enabled and (2) a second prespecified output speed when the compensation circuit is disabled; (D) a configuration circuit coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured to selectively output at the first prespecified output speed or second prespecified output speed.
Claim 2
Dependent Claim
110 words
A nonvolatile memory, comprising: (A) a memory array; (B) a buffer circuit for applying data read from the memory array to external circuitry; (C) a compensation circuit coupled to the buffer circuit form providing programmable output compensation to the buffer circuit when enabled, wherein the buffer circuit has (1) a first prespecified output speed when the compensation circuit is enabled and (2) a second prespecified output speed when the compensation circuit is disabled; (D) a configuration circuit coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured to selectively output at the first prespecified output speed or second prespecified output speed.
Claim 3
Dependent Claim
23 words
The nonvolatile memory of claim 1, wherein the configuration circuit detects a state of an address input to selectively enable the compensation circuit.
Claim 4
Dependent Claim
52 words
The nonvolatile memory of claim 2, wherein when the configuration circuit detects an elevated high voltage at the address input, the configuration circuit enables the compensation circuit, wherein when the configuration circuit does not detect the elevated high voltage at the address input, the configuration circuit does not enable the compensation circuit.
Claim 5
Dependent Claim
40 words
The nonvolatile memory of claim 3, wherein when the compensation circuit is enabled, the compensation circuit is disabled by the configuration circuit when the configuration circuit detects a power down signal at a power down input of the nonvolatile memory.
Claim 6
Dependent Claim
25 words
The nonvolatile memory of claim 4, wherein the elevated high voltage is approximately 12 volts, wherein the power down signal is a logical low signal.
Claim 7
Dependent Claim
19 words
The nonvolatile memory of claim 1, wherein the nonvolatile memory includes memory cells that are electrically programmable and erasable.
Claim 8
Dependent Claim
152 words
A nonvolatile memory, comprising: (A) a memory array; (B) a buffer circuit for applying data read from the memory array to external circuitry; (C) a compensation circuit coupled to the buffer circuit for providing programmable output compensation to the buffer circuit such that the buffer circuit has a first prespecified output speed, wherein the buffer circuit has a second prespecified output speed when the compensation circuit is disabled; (D) a configuration circuit coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured to selectively output at the first prespecified output speed or second prespecified output speed, further comprising (i) a high voltage detector for generating a high voltage indication signal when an elevated high voltage is applied to an address input; (ii) an enable circuit for enabling the compensation circuit in accordance with the high voltage indication signal from the high voltage detector.
Claim 9
Dependent Claim
152 words
A nonvolatile memory, comprising: (A) a memory array; (B) a buffer circuit for applying data read from the memory array to external circuitry; (C) a compensation circuit coupled to the buffer circuit for providing programmable output compensation to the buffer circuit such that the buffer circuit has a first prespecified output speed, wherein the buffer circuit has a second prespecified output speed when the compensation circuit is disabled; (D) a configuration circuit coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be configured to selectively output at the first prespecified output speed or second prespecified output speed, further comprising (i) a high voltage detector for generating a high voltage indication signal when an elevated high voltage is applied to an address input; (ii) an enable circuit for enabling the compensation circuit in accordance with the high voltage indication signal from the high voltage detector.
Claim 10
Dependent Claim
16 words
The nonvolatile memory of claim 7, wherein the enable circuit further comprises an edge triggered latch.
Claim 11
Dependent Claim
32 words
The nonvolatile memory of claim 8, wherein when the high voltage detector does not detect the elevated high voltage at the address input, the enable circuit does not enable the compensation circuit.
Claim 12
Dependent Claim
49 words
The nonvolatile memory of claim 9, wherein the latch is also coupled to a power down input of the nonvolatile memory, wherein the latch is reset by a power down signal applied at the power down input, where when the latch is reset, the latch disables the compensation circuit.
Claim 13
Dependent Claim
25 words
The nonvolatile memory of claim 10, wherein the elevated high voltage is approximately 12 volts, wherein the power down signal is a logical low signal.
Claim 14
Dependent Claim
19 words
The nonvolatile memory of claim 7, wherein the nonvolatile memory includes memory cells that are electrically programmable and erasable.
Claim 15
Dependent Claim
18 words
The nonvolatile memory of claim 7, wherein the address input is an A9 address bit of an address.
Claim 16
Independent Claim
114 words
A method of programmably configuring a nonvolatile memory between a first prespecified output speed and a second prespecified output speed, comprising the steps of: (A) detecting if an elevated high voltage is applied to an address input of the nonvolatile memory; (B) enabling a compensation circuit coupled to a buffer circuit of the nonvolatile memory to configure the nonvolatile memory with the first prespecified output speed if the elevated high voltage is applied to the address input of the nonvolatile memory; (C) not enabling the compensation circuit to configure the nonvolatile memory with the second prespecified output speed if the elevated high voltage is not applied to the address input of the nonvolatile memory.
Claim 17
Independent Claim
114 words
A method of programmably configuring a nonvolatile memory between a first prespecified output speed and a second prespecified output speed, comprising the steps of: (A) detecting if an elevated high voltage is applied to an address input of the nonvolatile memory; (B) enabling a compensation circuit coupled to a buffer circuit of the nonvolatile memory to configure the nonvolatile memory with the first prespecified output speed if the elevated high voltage is applied to the address input of the nonvolatile memory; (C) not enabling the compensation circuit to configure the nonvolatile memory with the second prespecified output speed if the elevated high voltage is not applied to the address input of the nonvolatile memory.
Claim 18
Dependent Claim
36 words
The method of claim 14, wherein the step (B) further comprises the step of disabling the compensation circuit, after the compensation circuit has been enabled, by causing the nonvolatile memory to enter a power down mode.
Claim 19
Dependent Claim
14 words
The method of claim 14, wherein the elevated high voltage is approximately 12 volts.
Claim 20
Dependent Claim
113 words
A computer system, comprising: (a) a microprocessor; (b) a nonvolatile memory, comprising: (A) a memory array; (B) a buffer circuit for applying data read from the memory array to external circuitry; (C) a compensation circuit coupled to the buffer circuit for providing programmable output compensation to the buffer circuit when enabled, wherein the buffer circuit has (1) a first prespecified output speed when the compensation circuit is enabled and (2) a second prespecified output speed when the compensation circuit is disabled; (D) a configuration circuit coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be selectively configured at the first and second prespecified output speeds.
Claim 21
Dependent Claim
113 words
A computer system, comprising: (a) a microprocessor; (b) a nonvolatile memory, comprising: (A) a memory array; (B) a buffer circuit for applying data read from the memory array to external circuitry; (C) a compensation circuit coupled to the buffer circuit for providing programmable output compensation to the buffer circuit when enabled, wherein the buffer circuit has (1) a first prespecified output speed when the compensation circuit is enabled and (2) a second prespecified output speed when the compensation circuit is disabled; (D) a configuration circuit coupled to the compensation circuit for selectively enabling the compensation circuit such that the buffer circuit can be selectively configured at the first and second prespecified output speeds.
Claim 22
Dependent Claim
23 words
The computer system of claim 17, wherein the configuration circuit detects the voltage of an address input to selectively enable the compensation circuit.
Claim 23
Dependent Claim
52 words
The computer system of claim 18, wherein when the configuration circuit detects an elevated high voltage at the address input, the configuration circuit enables the compensation circuit, wherein when the configuration circuit does not detect the elevated high voltage at the address input, the configuration circuit does not enable the compensation circuit.
Claim 24
Dependent Claim
40 words
The computer system of claim 19, wherein when the compensation circuit is enabled, the compensation circuit is disabled by the configuration circuit when the configuration circuit detects a power down signal at a power down input of the nonvolatile memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-24 | 2002-02-23 | 2002-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-24 | 2006-02-23 | 2006-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-24 | 2010-02-23 | 2010-08-25 | $7700.00 | Window Closed / Lapsed |