US5132566A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BiMOS semiconductor integrated circuit having short-circuit protection
Assignee: NEC Corp
•
Filing: 1990-07-25
•
Granted: 1992-07-21
•
Expires: 2010-07-25
Abstract
Abstract An output circuit capable of limiting an output current from a BiMOS semiconductor integrated circuit without adversely affecting an operational speed includes a plurality of bipolar transistors connected to form a Darlington circuit and at least one field effect transistor which can be either a P-channel or an N-channel transistor. The circuit is capable of removing rise current limitations of the bipolar transistors in the Darlington circuit during a normal operation by using a single MOS transistor to provide a branch circuit for the Darlington circuit, which limits the output current of the circuit under the specific condition that it provides a high level output and its output terminal is short-circuited to the ground.
Inventors
- 👤 Akira Denda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:57
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/08112
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
381 words
A BiMOS semiconductor integrated circuit comprising: a first power source voltage line for supplying a first power source voltage; a second power source voltage line for supplying a second power source voltage lower than said first power source voltage; an output node; a first resistor; a second resistor; a first bipolar transistor having a collector connected to said first power source voltage line, a base connected to said first power source voltage line through said first resistor, and an emitter connected to said output node through said second resistor; a second bipolar transistor including a collector connected to said first power source voltage line, a base connected to said emitter of said first bipolar transistor, and an emitter connected to said output node to form a Darlington circuit with said first bipolar transistor for providing a high level output at said output node in a high level outputting operation of said circuit; a third bipolar transistor having a collector connected to said output node and an emitter connected to said second power source voltage line for providing a low level output at said output node in a low level outputting operation of said circuit; and a P-channel field effect transistor formed on a N-well provided in a P-type substrate, said N-well being connected to said first power source voltage line, said P-channel field effect transistor having a source connected to said base of said first bipolar transistor, a drain connected to said output node, and a gate which with said emitter of said second bipolar transistor and said drain are commonly connected to said output node, wherein: threshold voltages of said P-channel field effect transistor in said high and low level outputting operations, and base-emitter forward voltages of said first and second bipolar transistors in said high and low level outputting operations in a normal state and in said high level outputting operations in an abnormal state in which said output node is short-circuited to said second power source voltage line are determined such that said P-channel field effect transistor maintains substantially OFF state when said circuit normally operates in said high and low level outputting operations, and turns ON only when said output node is abnormally short-circuited to said second power source voltage line in said high level outputting operation.
Claim 2
Dependent Claim
381 words
A BiMOS semiconductor integrated circuit comprising: a first power source voltage line for supplying a first power source voltage; a second power source voltage line for supplying a second power source voltage lower than said first power source voltage; an output node; a first resistor; a second resistor; a first bipolar transistor having a collector connected to said first power source voltage line, a base connected to said first power source voltage line through said first resistor, and an emitter connected to said output node through said second resistor; a second bipolar transistor including a collector connected to said first power source voltage line, a base connected to said emitter of said first bipolar transistor, and an emitter connected to said output node to form a Darlington circuit with said first bipolar transistor for providing a high level output at said output node in a high level outputting operation of said circuit; a third bipolar transistor having a collector connected to said output node and an emitter connected to said second power source voltage line for providing a low level output at said output node in a low level outputting operation of said circuit; and a P-channel field effect transistor formed on a N-well provided in a P-type substrate, said N-well being connected to said first power source voltage line, said P-channel field effect transistor having a source connected to said base of said first bipolar transistor, a drain connected to said output node, and a gate which with said emitter of said second bipolar transistor and said drain are commonly connected to said output node, wherein: threshold voltages of said P-channel field effect transistor in said high and low level outputting operations, and base-emitter forward voltages of said first and second bipolar transistors in said high and low level outputting operations in a normal state and in said high level outputting operations in an abnormal state in which said output node is short-circuited to said second power source voltage line are determined such that said P-channel field effect transistor maintains substantially OFF state when said circuit normally operates in said high and low level outputting operations, and turns ON only when said output node is abnormally short-circuited to said second power source voltage line in said high level outputting operation.
Claim 3
Dependent Claim
26 words
A BiMOS semiconductor integrated circuit as claimed in claim 1, wherein said first and second bipolar transistors forming said Darlington circuit are NPN type bipolar transistors.
Claim 4
Dependent Claim
30 words
A BiMOS semiconductor integrated circuit as claimed in claim 1, wherein said first power source voltage is a positive voltage, and said second power source voltage is a ground voltage.
Claim 5
Dependent Claim
23 words
A BiMOS semiconductor integrated circuit as claimed in claim 1, wherein said P-type substrate is connected to said second power source voltage line.
Claim 6
Dependent Claim
374 words
A BiMOS semiconductor integrated circuit comprising: a first power source voltage line for supplying a first power source voltage; a second power source voltage line for supplying a second power source voltage lower than said first power source voltage; an output node; a first resistor; a second resistor; a first bipolar transistor having a collector connected to said first power source voltage line, a base connected to said first power source voltage line through said first resistor, and an emitter connected to said output node through said second resistor; a second bipolar transistor having a collector connected to said first power source voltage line, a base connected to said emitter of said first bipolar transistor, and an emitter connected to said output node to form a Darlington circuit with said first bipolar transistor for providing a high level output at said output node in a high level outputting operation of said circuit; a third bipolar transistor having a collector connected to said output node and an emitter connected to said second power source voltage line for providing a low level output at said output node in a low level outputting operation of said circuit; an N-channel field effect transistor formed on a P-well provided in a P-type substrate, said P-well being connected to said second power source voltage line, said N-channel field effect transistor having a source connected to said output node, a drain connected to said base of said first bipolar transistor, and a gate commonly connected with said drain to said base of said first bipolar transistor, wherein threshold voltages of said N-channel field effect transistor in said high and low level outputting operations, and base-emitter forward voltages of said first and second bipolar transistors in said high and low level outputting operations in a normal state and in said high level outputting operation in an abnormal state in which said output node is short-circuited to said second power source voltage line are determined such that said N-channel field effect transistor maintains substantially OFF state when said circuit normally operates in said high and low level outputting operations and turns ON only when said output node is abnormally short-circuited to said second power source voltage line in said high level outputting operations.
Claim 7
Dependent Claim
374 words
A BiMOS semiconductor integrated circuit comprising: a first power source voltage line for supplying a first power source voltage; a second power source voltage line for supplying a second power source voltage lower than said first power source voltage; an output node; a first resistor; a second resistor; a first bipolar transistor having a collector connected to said first power source voltage line, a base connected to said first power source voltage line through said first resistor, and an emitter connected to said output node through said second resistor; a second bipolar transistor having a collector connected to said first power source voltage line, a base connected to said emitter of said first bipolar transistor, and an emitter connected to said output node to form a Darlington circuit with said first bipolar transistor for providing a high level output at said output node in a high level outputting operation of said circuit; a third bipolar transistor having a collector connected to said output node and an emitter connected to said second power source voltage line for providing a low level output at said output node in a low level outputting operation of said circuit; an N-channel field effect transistor formed on a P-well provided in a P-type substrate, said P-well being connected to said second power source voltage line, said N-channel field effect transistor having a source connected to said output node, a drain connected to said base of said first bipolar transistor, and a gate commonly connected with said drain to said base of said first bipolar transistor, wherein threshold voltages of said N-channel field effect transistor in said high and low level outputting operations, and base-emitter forward voltages of said first and second bipolar transistors in said high and low level outputting operations in a normal state and in said high level outputting operation in an abnormal state in which said output node is short-circuited to said second power source voltage line are determined such that said N-channel field effect transistor maintains substantially OFF state when said circuit normally operates in said high and low level outputting operations and turns ON only when said output node is abnormally short-circuited to said second power source voltage line in said high level outputting operations.
Claim 8
Dependent Claim
26 words
A BiMOS semiconductor integrated circuit as claimed in claim 5, wherein said first and second bipolar transistors forming said Darlington circuit are NPN type bipolar transistors.
Claim 9
Dependent Claim
30 words
A BiMOS semiconductor integrated circuit as claimed in claim 5, wherein said first power source voltage is a positive voltage, and said second power source voltage is a ground voltage.
Claim 10
Dependent Claim
22 words
A BiMOS semiconductor integrated circuit as claimed in claim 5, wherein said P-type substrate is connected to said power source voltage line.
References Cited (Backward Citations)
US4424455A
Cited
US4791320A
Cited
US4638186A
Cited
US4649294A
Cited
US4760433A
Cited
US4746817A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |