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US5797035A
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Networked multiprocessor system with global distributed memory and block transfer engine
Assignee: Morgan Stanley and Co LLC
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Filing: 1996-06-12
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Granted: 1998-08-18
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Expires: 2016-06-12
Abstract
Abstract A multidimensional interconnection and routing apparatus for a parallel processing computer connects together possessing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
Inventors
- 👤 Mark S. Birrittella
- 👤 Richard E. Kessler
- 👤 Steven M. Oberlin
- 👤 Randal S. Passint
- 👤 Greg Thorson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:35
CPC Classifications
H; H04; H04L; H04L45/00; H04L45/02; H04L45/06; G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17356; G06F15/17368; G06F15/17381; H04L45/10; H04L49/00; H04L49/10; H04L49/101; H04L49/20; H04L49/205; H04L49/25; H04L49/251
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
111 words
A multiprocessor computer system, comprising: a plurality of processing element nodes, each node comprising: a processing element having a processor and a local memory, wherein globally addressable portions of local memory of each processing element form a distributed memory, and a block transfer engine for redistributing data between the globally addressable portions of local memory without interrupting the associated processors; a host communication path for connecting at least one of the processing elements with a host system; and an interconnection network connecting together the processing element nodes in an n-dimensional topology, the network comprising internode communication paths connecting each of the plurality of processing element nodes to adjacent processing element nodes.
Claim 2
Dependent Claim
111 words
A multiprocessor computer system, comprising: a plurality of processing element nodes, each node comprising: a processing element having a processor and a local memory, wherein globally addressable portions of local memory of each processing element form a distributed memory, and a block transfer engine for redistributing data between the globally addressable portions of local memory without interrupting the associated processors; a host communication path for connecting at least one of the processing elements with a host system; and an interconnection network connecting together the processing element nodes in an n-dimensional topology, the network comprising internode communication paths connecting each of the plurality of processing element nodes to adjacent processing element nodes.
Claim 3
Dependent Claim
76 words
The multiprocessor computer system of claim 1 wherein each of the processing element nodes further comprises: a network interface coupled to the processing element, the block transfer engine and the interconnection network, each network interface generating packets of information by formatting information provided from the processing element or the block transfer engine to be sent to another processing element node, and receiving the packets of information generated by other network interfaces in other processing element nodes.
Claim 4
Dependent Claim
62 words
The multiprocessor computer system of claim 2 wherein the interconnection network further comprises a plurality of network routers, each of the network routers coupled between the network interface for a particular processing element node and the internode communication paths for the particular processing element node, the network routers transferring the packets of information generated by the network interfaces though the interconnect network.
Claim 5
Dependent Claim
173 words
The multiprocessor computer system of claim 3 wherein each of the network routers comprises n dimension switches, each being associated with a corresponding one of the n dimensions to control the transferring of the packets of information from the corresponding one of the n dimensions, the n dimension switches including: a first dimension switch associated with a first of the n dimensions, and coupled to the corresponding network interface and the internode communication paths along first and second directions in the first of the n dimensions for the corresponding processing element node, and controlling the transferring of the packets of information from the first of the n dimensions internode communication paths; and a second dimension switch associated with a second of the n dimensions, and coupled to the first dimension switch and the internode communication paths along first and second directions in the second of the n dimensions for the corresponding processing element node, and controlling the transferring of the packets of information from the second of the n dimensions internode communication paths.
Claim 6
Dependent Claim
27 words
The multiprocessor computer system of claim 1 wherein the interconnection network interleaves the processing element nodes to minimize the maximum interconnection distance between the processing element nodes.
Claim 7
Dependent Claim
48 words
The multiprocessor computer system of claim 1 wherein the interconnection network further comprises a plurality of virtual channel buffers storing request and response information communicated between the processing element nodes over the internode communication paths, each of the virtual channel buffers coupled to one of the processing elements.
Claim 8
Dependent Claim
37 words
The multiprocessor computer system of claim 6 wherein the interconnection network further comprises means for arbitrating between conflicts between virtual channel buffers by assigning separate priorities to each virtual channel buffer coupled to a particular processing element.
Claim 9
Dependent Claim
51 words
The multiprocessor computer system of claim 7 wherein the means for arbitrating includes: free running priority counters which provide priority bits indicative of the priorities assigned to each virtual channel buffer; and a random number generator coupled to the priority counters to generate disable pulses which randomly disable the priority counters.
Claim 10
Dependent Claim
73 words
The multiprocessor computer system of claim 4 wherein each of the n dimension switches includes input channels to receive the packets of information from the internode communication paths and output channels to transfer the packets of information from the n dimensional switch to the internode communication paths, and wherein each dimension switch includes means for arbitrating between input channel conflicts by assigning separate priorities to each input channel in the n dimension switch.
Claim 11
Dependent Claim
50 words
The multiprocessor computer system of claim 9 wherein the means for arbitrating includes: free running priority counters which provide priority bits indicative of the priorities assigned to each input channel; and a random number generator coupled to the priority counters to generate disable pulses which randomly disable the priority counters.
Claim 12
Dependent Claim
30 words
The multiprocessor computer system of claim 1 wherein each processing element node comprises a second processing element, and wherein the block transfer engine is coupled between the two processing elements.
Claim 13
Dependent Claim
51 words
The multiprocessor computer system of claim 2 wherein the network interface comprises means for formatting information from the processing element or the block transfer engine to be provided to the host system on the host communication path and means for receiving information from the host system via the host communication path.
Claim 14
Dependent Claim
55 words
The multiprocessor computer system of claim 1 wherein the host communication path comprises an I/O gateway having an input node receiving and transferring incoming system data from the host system to the processing element nodes and having an output node retrieving and transmitting outgoing system data from the processing element nodes to the host system.
Claim 15
Dependent Claim
37 words
The multiprocessor computer system of claim 13 wherein the input node includes high speed input circuitry to receive the incoming system data, and the output node includes high speed output circuitry to transmit the outgoing system data.
Claim 16
Dependent Claim
46 words
The multiprocessor computer system of claim 14 wherein the I/O gateway further includes low speed circuitry communicating request and response information to and from the host system to control the transfer of system data over the high speed input circuitry and the high speed output circuitry.
Claim 17
Dependent Claim
49 words
The multiprocessor computer system of claim 14 wherein the input node includes a processing element and a block transfer engine to interface with the high speed input circuitry, and the output node includes a processing element and a block transfer engine to interface with the high speed output circuitry.
Claim 18
Dependent Claim
73 words
The multiprocessor computer system of claim 16 wherein the input node includes a network interface generating packets of information by formatting system information provided from the input node's processing element or block transfer engine to be transferred to the processing element nodes, and the output node includes a network interface retrieving packets of system information from the processing element nodes to be provided to the output node's processing element or block transfer engine.
Claim 19
Dependent Claim
47 words
The multiprocessor computer system of claim 17 wherein the input and output nodes each include a network router coupled between their respective network interface and system communication paths connecting the I/O gateway to the interconnection network to transfer packets of system information over the system communication paths.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |