Apparatus and method of preventing a deadlock condition in a computer system

Claim 2

A circuit for preventing deadlock between a microprocessor coupled to a first bus and a bus master coupled to a second bus, wherein the microprocessor has data and address outputs for connection to the first bus and has cycle control outputs, and wherein the first bus has data and address portions and is coupled to a resource, the circuit comprising: first means for receiving the microprocessor cycle control outputs to determine a request by the microprocessor for a microprocessor-to-second-bus cycle, wherein the microprocessor continuously drives or controls its address, data, and control cycle outputs once it starts said microprocessor-to-second-bus cycle; second means for receiving a request from the second bus master for the first bus resource; means coupled to said first and second receiving means for generating a float signal, said float signal being asserted if said microprocessor-to-second-bus cycle request is pending when said second bus master request is asserted; and a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between the microprocessor data and address outputs and said first bus data and address portions, said plurality of tristate buffers being disabled if said float signal is asserted, wherein said tristate buffers are implemented with bi-directional high speed bus switches.

Claim 3

The circuit of claim 1, further comprising: means coupled to said second receiving means and said float signal generating means for executing said second bus master request after said float signal is asserted and for asserting a complete signal when done, wherein said float signal generating means deasserts said float signal after said complete signal is asserted; and means responsive to said complete signal for completing said microprocessor-to-second-bus cycle after said complete signal is asserted.

Claim 4

The circuit of claim 1, wherein the microprocessor is a 80386-type processor.

Claim 5

The circuit of claim 3, wherein the microprocessor is a 386EX processor.

Claim 6

The circuit of claim 1, wherein the second bus is a PCI bus.

Claim 7

The circuit of claim 5, wherein the second bus master is an expansion bus bridge for connection between said PCI bus and an expansion bus, said expansion bus being connected to an expansion bus master, wherein said expansion bus bridge asserts a request for the first bus resource in response to said expansion bus master asserting a request for the first bus resource.

Claim 8

The circuit of claim 6, wherein said expansion bus is an EISA bus.

Claim 9

The circuit of claim 6, wherein the microprocessor is a 80386-type processor.

Claim 10

The circuit of claim 8, wherein the microprocessor is a 386EX processor.

Claim 11

A circuit for preventing deadlock between a microprocessor coupled to a first bus and a bus master coupled to a second bus, wherein the microprocessor has data and address outputs for connection to the first bus and has cycle control outputs, and wherein the first bus has data and address portions and is coupled to a resource, the circuit comprising: first means for receiving the microprocessor cycle control outputs to determine a request by the microprocessor for a microprocessor-to-second bus cycle, wherein the microprocessor continuously drives or controls its address, data, and control cycle outputs once it starts said microprocessor-to-second-bus cycle; second means for receiving a request from the second bus master for the first bus resource; means coupled to said first and second receiving means for generating a float signal, said float signal being asserted if said microprocessor-to-second-bus cycle request is pending when said second bus master request is asserted; and a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between the microprocessor data and address outputs and said first bus data and address portions, said plurality of tristate buffers being disabled if said float signal is asserted, wherein the first bus is further coupled to a first bus slave device, the microprocessor capable of generating a read cycle and a write cycle on the first bus, wherein said first bus slave device drives said first bus data portion in response to a read cycle directed to said first bus slave device, and wherein said float signal generating means asserts said float signal for a predetermined amount of time after a microprocessor read cycle is complete to avoid data contention between a subsequent microprocessor write cycle and read data driven by said first bus slave device.

Claim 12

A circuit for preventing deadlock between a microprocessor coupled to a first bus and a bus master coupled to a second bus, wherein the microprocessor has data and address outputs for connection to the first bus and has cycle control outputs, and wherein the first bus has data and address portions and is coupled to a resource, the circuit comprising: first means for receiving the microprocessor cycle control outputs to determine a request by the microprocessor for a microprocessor-to-second bus cycle, wherein the microprocessor continuously drives or controls its address, data, and control cycle outputs once it starts said microprocessor-to-second-bus cycle; second means for receiving a request from the second bus master for the first bus resource; means coupled to said first and second receiving means for generating a float signal, said float signal being asserted if said microprocessor-to-second-bus cycle request is pending when said second bus master request is asserted; and a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between the microprocessor data and address outputs and said first bus data and address portions, said plurality of tristate buffers being disabled if said float signal is asserted, wherein the first bus is further coupled to a first bus slave device, the microprocessor capable of generating a read cycle and a write cycle on the first bus, wherein said first bus slave device drives said first bus data portion in response to a read cycle directed to said first bus slave device, and wherein said float signal generating means asserts said float signal for a predetermined amount of time after a microprocessor read cycle is complete to avoid data contention between a subsequent microprocessor write cycle and read data driven by said first bus slave device.

Claim 13

A computer system, comprising: a first bus having data and address portions; a processor unit coupled to said first bus, said processor unit receiving a float signal and having address, data and cycle control output pins, said processor unit further including an 80386-type microprocessor, said processor unit address and data output pins being connected to said first bus address and data portions; a bus resource coupled to said first bus; a second bus; a second bus master coupled to said second bus; and a circuit coupled to said first and second buses, including: first means for receiving the processor cycle control output pins to determine a request by said processor unit for a processor-to-second-bus cycle, wherein said processor unit continuously drives or controls its address, data, and cycle control output pins once it starts said processor-to-second-bus cycle; second means for receiving a request from said second bus master for said first bus resource; and means coupled to said first and second receiving means for generating said float signal, said float signal being asserted if said processor-to-second-bus cycle request is pending when said second bus master request is asserted, wherein if said float signal is asserted, said processor unit floats its address and data output pins and continues to drive the cycle control output pins, wherein said processor unit further includes a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor data and address outputs and said processor unit data and address output pins, said plurality of tristate buffers being disabled if said float signal is asserted, and wherein said tristate buffers are implemented with bidirectional high speed bus switches.

Claim 14

A computer system, comprising: a first bus having data and address portions; a processor unit coupled to said first bus, said processor unit receiving a float signal and having address, data and cycle control output pins, said processor unit further including an 80386-type microprocessor, said processor unit address and data output pins being connected to said first bus address and data portions; a bus resource coupled to said first bus; a second bus; a second bus master coupled to said second bus; and a circuit coupled to said first and second buses, including: first means for receiving the processor cycle control output pins to determine a request by said processor unit for a processor-to-second-bus cycle, wherein said processor unit continuously drives or controls its address, data, and cycle control output pins once it starts said processor-to-second-bus cycle; second means for receiving a request from said second bus master for said first bus resource; and means coupled to said first and second receiving means for generating said float signal, said float signal being asserted if said processor-to-second-bus cycle request is pending when said second bus master request is asserted, wherein if said float signal is asserted, said processor unit floats its address and data output pins and continues to drive the cycle control output pins, wherein said processor unit further includes a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor data and address outputs and said processor unit data and address output pins, said plurality of tristate buffers being disabled if said float signal is asserted, and wherein said tristate buffers are implemented with bidirectional high speed bus switches.

Claim 15

The circuit of claim 11, further comprising: means coupled to said second receiving means and said float signal generating means for executing said second bus master request after said float signal is asserted and for asserting a complete signal when done, wherein said float signal generating means deasserts said float signal after said complete signal is asserted; and means responsive to said complete signal for completing said processor-to-second-bus cycle after said complete signal is asserted.

Claim 16

The computer system of claim 11, wherein said 80386-type microprocessor is a 386EX microprocessor.

Claim 17

A computer system, comprising: a first bus having data and address portions; a microprocessor coupled to said first bus and having address, data and cycle control outputs; a bus resource coupled to said first bus; a second bus; a second bus master coupled to said second bus; and a circuit coupled to said first and second buses, including: first means for receiving said cycle control outputs to determine a request by said microprocessor for a microprocessor-to-second-bus cycle, wherein said microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts said microprocessor-to-second-bus cycle; second means for receiving a request from said second bus master for said first bus resource; means coupled to said first and second receiving means for generating a float signal, said float signal being asserted if said microprocessor-to-second-bus cycle request is pending when said second bus master request is asserted; and a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor data and address outputs and said first bus data and address portions, said plurality of tristate buffers being disabled if said float signal is asserted, wherein said tristate buffers are implemented with bi-directional high speed bus switches.

Claim 18

A computer system, comprising: a first bus having data and address portions; a microprocessor coupled to said first bus and having address, data and cycle control outputs; a bus resource coupled to said first bus; a second bus; a second bus master coupled to said second bus; and a circuit coupled to said first and second buses, including: first means for receiving said cycle control outputs to determine a request by said microprocessor for a microprocessor-to-second-bus cycle, wherein said microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts said microprocessor-to-second-bus cycle; second means for receiving a request from said second bus master for said first bus resource; means coupled to said first and second receiving means for generating a float signal, said float signal being asserted if said microprocessor-to-second-bus cycle request is pending when said second bus master request is asserted; and a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor data and address outputs and said first bus data and address portions, said plurality of tristate buffers being disabled if said float signal is asserted, wherein said tristate buffers are implemented with bi-directional high speed bus switches.

Claim 19

The computer system of claim 14, further comprising: means coupled to said second receiving means and said float signal generating means for executing said second bus master request after said float signal is asserted and for asserting a complete signal when done, wherein said float signal generating means deasserts said float signal after said complete signal is asserted; and means responsive to said complete signal for completing said processor-to-second-bus cycle after said complete signal is asserted.

Claim 20

The computer system of claim 14, wherein said microprocessor is a 80386-type processor.

Claim 21

The computer system of claim 16, wherein said microprocessor is a 386EX processor.

Claim 22

The computer system of claim 14, wherein said second bus is a PCI bus.

Claim 23

The computer system of claim 18, wherein said second bus master is an expansion bus bridge for connection between said PCI bus and an expansion bus, said expansion bus being connected to an expansion bus master, wherein said expansion bus bridge asserts a request for said first bus resource in response to said expansion bus master asserting a request for said first bus resource.

Claim 24

The computer system of claim 19, wherein said expansion bus is an EISA bus.

Claim 25

The computer system of claim 19, wherein said microprocessor is a 80386-type processor.

Claim 26

The computer system of claim 21, wherein said microprocessor is a 386EX processor.

Claim 27

A computer system, comprising: a first bus having data and address portions; a microprocessor coupled to said first bus and having address, data and cycle control outputs; a bus resource coupled to said first bus; a second bus; a second bus master coupled to said second bus; and a circuit coupled to said first and second buses, including: first means for receiving said cycle control outputs to determine a request by said microprocessor for a microprocessor-to-second-bus cycle, wherein said microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts said microprocessor-to-second-bus cycle; second means for receiving a request from said second bus master for said first bus resource; means coupled to said first and second receiving means for generating a float signal, said float signal being asserted if said microprocessor-to-second-bus cycle request is pending when said second bus master request is asserted; and a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor data and address outputs and said first bus data and address portions, said plurality of tristate buffers being disabled if said float signal is asserted, wherein said first bus is further coupled to a first bus slave device, said microprocessor capable of generating a read cycle and a write cycle on said first bus, wherein said first bus slave device drives said first bus data portion in response to a read cycle directed to said first bus slave device, and wherein said float signal generating means asserts said float signal for a predetermined amount of time after a microprocessor read cycle is complete to avoid data contention between a subsequent microprocessor write cycle and read data driven by said first bus slave device.

Claim 28

A computer system, comprising: a first bus having data and address portions; a microprocessor coupled to said first bus and having address, data and cycle control outputs; a bus resource coupled to said first bus; a second bus; a second bus master coupled to said second bus; and a circuit coupled to said first and second buses, including: first means for receiving said cycle control outputs to determine a request by said microprocessor for a microprocessor-to-second-bus cycle, wherein said microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts said microprocessor-to-second-bus cycle; second means for receiving a request from said second bus master for said first bus resource; means coupled to said first and second receiving means for generating a float signal, said float signal being asserted if said microprocessor-to-second-bus cycle request is pending when said second bus master request is asserted; and a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor data and address outputs and said first bus data and address portions, said plurality of tristate buffers being disabled if said float signal is asserted, wherein said first bus is further coupled to a first bus slave device, said microprocessor capable of generating a read cycle and a write cycle on said first bus, wherein said first bus slave device drives said first bus data portion in response to a read cycle directed to said first bus slave device, and wherein said float signal generating means asserts said float signal for a predetermined amount of time after a microprocessor read cycle is complete to avoid data contention between a subsequent microprocessor write cycle and read data driven by said first bus slave device.

Claim 31

The method of claim 24, wherein the microprocessor is a 80386-type processor.

Claim 32

The method of claim 25, wherein the microprocessor is a 386EX processor.

Claim 33

The method of claim 24, wherein the second bus is a PCI bus.

Claim 34

The method of claim 27, wherein the second bus master is an expansion bus bridge for connection between said PCI bus and an expansion bus, said expansion bus being connected to an expansion bus master, wherein said expansion bus bridge asserts a request for the first bus resource in response to said expansion bus master asserting a request for the first bus resource.

Claim 35

The method of claim 28, wherein said expansion bus is an EISA bus.

Claim 36

The method of claim 29, wherein the microprocessor is a 80386-type processor.

Claim 37

The method of claim 30, wherein the microprocessor is a 386EX processor.

Claim 38

A microprocessor having address, data and cycle control output pins and receiving a float signal, the microprocessor comprising: a microprocessor core having address, data, and cycle control outputs, wherein said microprocessor core continuously drives or controls its address, data, and cycle control outputs once it starts a cycle; and means coupled to said microprocessor core address, data and cycle control outputs for coupling said microprocessor core address, data and cycle control outputs to said microprocessor address, data and cycle control output pins, said means receiving the float signal, wherein if the float signal is asserted, said means floats said microprocessor address and data output pins and continues to drive said microprocessor cycle control output pins, wherein said coupling means includes a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor core data and address outputs and said microprocessor data and address output pins, said plurality of tristate buffers being disabled if said float signal is asserted, and wherein said tristate buffers are implemented with bi-directional high speed bus switches.

Claim 39

A microprocessor having address, data and cycle control output pins and receiving a float signal, the microprocessor comprising: a microprocessor core having address, data, and cycle control outputs, wherein said microprocessor core continuously drives or controls its address, data, and cycle control outputs once it starts a cycle; and means coupled to said microprocessor core address, data and cycle control outputs for coupling said microprocessor core address, data and cycle control outputs to said microprocessor address, data and cycle control output pins, said means receiving the float signal, wherein if the float signal is asserted, said means floats said microprocessor address and data output pins and continues to drive said microprocessor cycle control output pins, wherein said coupling means includes a plurality of tristate buffers responsive to said float signal, said tristate buffers being connected between said microprocessor core data and address outputs and said microprocessor data and address output pins, said plurality of tristate buffers being disabled if said float signal is asserted, and wherein said tristate buffers are implemented with bi-directional high speed bus switches.

Claim 40

The microprocessor of claim 32, wherein said microprocessor is an 80386-type microprocessor.

Claim 41

The microprocessor of claim 33, wherein said 80386-type microprocessor is a 386EX microprocessor.

Claim 42

A computer system, comprising: a first bus having data and address portions; a second bus; a storage system coupled to the first bus or the second bus; a microprocessor coupled to the first bus, the microprocessor having address, data, and cycle control outputs, wherein the microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts a microprocessor-to-second-bus cycle; a first bus resource coupled to the first bus; a second bus master coupled to the second bus; and a deadlock prevention circuit, including: a plurality of bi-directional high speed bus switches connected between the microprocessor data and address outputs and the first bus data and address portions; microprocessor-to-second-bus cycle decode logic coupled to the microprocessor cycle control outputs and decoding a pending microprocessor-to-second-bus cycle; second bus master to first bus resource decode logic coupled to the second bus master via the second bus and decoding a request from the second bus master for the first bus resource; and switch control logic coupled to and controlling the plurality of bi-directional high speed bus switches responsive to the microprocessor-to-second-bus cycle decode logic and the second bus master to first bus resource logic, the switch control logic disabling the switches when a microprocessor-to-second-bus cycle is pending while the second bus master is requesting the first bus resource.

Claim 43

A computer system, comprising: a first bus having data and address portions; a second bus; a storage system coupled to the first bus or the second bus; a microprocessor coupled to the first bus, the microprocessor having address, data, and cycle control outputs, wherein the microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts a microprocessor-to-second-bus cycle; a first bus resource coupled to the first bus; a second bus master coupled to the second bus; and a deadlock prevention circuit, including: a plurality of bi-directional high speed bus switches connected between the microprocessor data and address outputs and the first bus data and address portions; microprocessor-to-second-bus cycle decode logic coupled to the microprocessor cycle control outputs and decoding a pending microprocessor-to-second-bus cycle; second bus master to first bus resource decode logic coupled to the second bus master via the second bus and decoding a request from the second bus master for the first bus resource; and switch control logic coupled to and controlling the plurality of bi-directional high speed bus switches responsive to the microprocessor-to-second-bus cycle decode logic and the second bus master to first bus resource logic, the switch control logic disabling the switches when a microprocessor-to-second-bus cycle is pending while the second bus master is requesting the first bus resource.

Claim 44

The circuit of claim 35, wherein the microprocessor is a 80386-type processor.

Claim 45

The circuit of claim 36, wherein the microprocessor is a 386EX processor.

Claim 46

The circuit of claim 35, wherein the second bus is a PCI bus.

Claim 47

The circuit of claim 38, wherein the second bus master is an expansion bus bridge for connection between said PCI bus and an expansion bus, said expansion bus being connected to an expansion bus master, wherein said expansion bus bridge asserts a request for the first bus resource in response to said expansion bus master asserting a request for the first bus resource.

Claim 48

The circuit of claim 39, wherein said expansion bus is an EISA bus.

Claim 49

The circuit of claim 39, wherein the microprocessor is a 80386-type processor.

Claim 50

The circuit of claim 39, wherein the microprocessor is a 386EX processor.

Claim 51

A computer system, comprising: a first bus having data and address portions; a second bus; a storage system coupled to the first bus or the second bus; a microprocessor coupled to the first bus, the microprocessor having address, data, and cycle control outputs, wherein the microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts a microprocessor-to-second-bus cycle, and wherein the microprocessor can generate a read cycle and a write cycle on the first bus; a first bus resource coupled to the first bus; a second bus master coupled to the second bus; a first bus slave device coupled to the first bus, the first bus slave device driving the data portion of the first bus in response to a microprocessor read cycle; and a deadlock prevention circuit, including: a plurality of tristate buffers connected between the microprocessor data and address outputs and the first bus data and address portions; microprocessor-to-second-bus cycle decode logic coupled to the microprocessor cycle control outputs and decoding a pending microprocessor-to-second-bus cycle; second-bus-master-to-first-bus-resource decode logic coupled to the second bus master via the second bus and decoding a request from the second bus master for the first bus resource; and switch control logic coupled to and controlling the plurality of tristate buffers responsive to the microprocessor-to-second-bus cycle decode logic and the second-bus-master-to-first-bus-resource decode logic, the switch control logic turning off the tristate buffers when a microprocessor-to-second-bus cycle is pending while the second bus master is requesting the first bus resource, and the switch control logic turning off the tristate buffer for a predetermined amount of time after a microprocessor read cycle is complete to avoid data contention between a subsequent microprocessor write cycle and read data driven by the first bus slave device.

Claim 52

A computer system, comprising: a first bus having data and address portions; a second bus; a storage system coupled to the first bus or the second bus; a microprocessor coupled to the first bus, the microprocessor having address, data, and cycle control outputs, wherein the microprocessor continuously drives or controls its address, data, and cycle control outputs once it starts a microprocessor-to-second-bus cycle, and wherein the microprocessor can generate a read cycle and a write cycle on the first bus; a first bus resource coupled to the first bus; a second bus master coupled to the second bus; a first bus slave device coupled to the first bus, the first bus slave device driving the data portion of the first bus in response to a microprocessor read cycle; and a deadlock prevention circuit, including: a plurality of tristate buffers connected between the microprocessor data and address outputs and the first bus data and address portions; microprocessor-to-second-bus cycle decode logic coupled to the microprocessor cycle control outputs and decoding a pending microprocessor-to-second-bus cycle; second-bus-master-to-first-bus-resource decode logic coupled to the second bus master via the second bus and decoding a request from the second bus master for the first bus resource; and switch control logic coupled to and controlling the plurality of tristate buffers responsive to the microprocessor-to-second-bus cycle decode logic and the second-bus-master-to-first-bus-resource decode logic, the switch control logic turning off the tristate buffers when a microprocessor-to-second-bus cycle is pending while the second bus master is requesting the first bus resource, and the switch control logic turning off the tristate buffer for a predetermined amount of time after a microprocessor read cycle is complete to avoid data contention between a subsequent microprocessor write cycle and read data driven by the first bus slave device.