US5592509A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transceiver circuit with transition detection
Assignee: Texas Instruments Inc
•
Filing: 1995-06-07
•
Granted: 1997-01-07
•
Expires: 2015-06-07
Abstract
Abstract A bidirectional data transceiver circuit is described which automatically transfers data from a first bidirectional data port to a second bidirectional data port when new data is detected. The transceiver has a collision arbitration circuit which prevents the device from driving data onto a data port that is being driven externally. An additional embodiment is described wherein the transition detection circuitry of the transceiver is used to provide a input transition detection flag for an integrated circuit having standby or low power modes. An integrated circuit providing an array of the transceivers of the invention is described. A transceiver which automatically detects a transition in data and provides output drive for data busses is described. Other devices, systems and methods are also described.
Inventors
- 👤 Mark T. McClear
- 👤 Christopher Wellheuser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:49
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/028; H04L25/0292; H04L25/20; H04L25/24; H04L25/242; H04L5/00; H04L5/14; H04L5/16; H04L25/029; H04L25/0298
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
207 words
An integrated circuit, comprising: a first bidirectional data port; a second bidirectional data port; and a plurality of transceivers coupled to said first and second bidirectional data ports, each of said transceivers comprising: a first bus holder circuit coupled to said first bidirectional data port; a second bus holder circuit coupled to said second bidirectional data port; a first tri-state output driver coupled to said second bidirectional data port; a second tri-state output driver coupled to said first bidirectional data port; a first input transition detector coupled to said first bus holder circuit comprising a rising edge detector circuit and a falling edge detector circuit and outputting a first edge detection signal when either a rising or falling edge is detected; a second input transition detector coupled to said second bus holder circuit comprising a rising edge detector circuit and a falling edge detector circuit and outputting a second edge detection signal when either a rising or falling edge is detected; collision arbitration circuitry coupled to said first and second input transition detectors and having outputs for enabling said first and second tri-state output drivers to transmit data on said second and first bidirectional data ports, respectively, responsive to said first and second edge detection signals, respectively.
Claim 2
Dependent Claim
207 words
An integrated circuit, comprising: a first bidirectional data port; a second bidirectional data port; and a plurality of transceivers coupled to said first and second bidirectional data ports, each of said transceivers comprising: a first bus holder circuit coupled to said first bidirectional data port; a second bus holder circuit coupled to said second bidirectional data port; a first tri-state output driver coupled to said second bidirectional data port; a second tri-state output driver coupled to said first bidirectional data port; a first input transition detector coupled to said first bus holder circuit comprising a rising edge detector circuit and a falling edge detector circuit and outputting a first edge detection signal when either a rising or falling edge is detected; a second input transition detector coupled to said second bus holder circuit comprising a rising edge detector circuit and a falling edge detector circuit and outputting a second edge detection signal when either a rising or falling edge is detected; collision arbitration circuitry coupled to said first and second input transition detectors and having outputs for enabling said first and second tri-state output drivers to transmit data on said second and first bidirectional data ports, respectively, responsive to said first and second edge detection signals, respectively.
References Cited (Backward Citations)
US4630284A
Cited
US4700342A
Cited
US4756006A
Cited
US4888764A
Cited
US4825107A
Cited
US4825107B1
Cited
US4942317A
Cited
US4980580A
Cited
US5243623A
Cited
US5216667A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |