US5596725A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fifo queue having replaceable entries
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-02-14
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Granted: 1997-01-21
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Expires: 2014-02-14
Abstract
Abstract A FIFO queue is utilized to provide control information to the appropriate time slot in a time multiplexed serial link between an interface chip and a CODEC. The FIFO queue allows rewriting or replacement of any control registers present in the queue without requiring that a new entry be placed in the queue. A particular control register which is placed in the queue then maintains its place as the queue is emptied, even though the control register may be written one or more times while the control register entry is in the queue waiting for transmission to the CODEC. The loss of the prior command information is not a problem as the data rate of the serial link is still sufficiently high so that any minor transitory change which may have been desired would be of minimal effect in any regard and would have been inaudible to the human.
Inventors
- 👤 Patrick L. Ferguson
- 👤 David J. Maguire
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:09
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F7/00; G06F2205/00; G06F2205/06; G06F2205/062
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
352 words
A circuit for transferring data from a first device to a second device, wherein the first device performs a write operation to transfer data, the circuit comprising: a plurality of registers addressable by the first device for storing data to be transferred from the first device to the second device; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation detection circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from a register, indicated among by the register address at the top of said FIFO queues, to the second device; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided; said data provision circuit further performing a parallel to serial conversion of said data; and a time multiplexed serial link connected to the second device, said time multiplexed serial link having a plurality of time slots, one of said time slots being a designated time slot to receive data from said plurality of registers; and said data provision circuit performing said parallel to serial conversion during said designated time slot of said time multiplexed serial link.
Claim 2
Dependent Claim
352 words
A circuit for transferring data from a first device to a second device, wherein the first device performs a write operation to transfer data, the circuit comprising: a plurality of registers addressable by the first device for storing data to be transferred from the first device to the second device; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation detection circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from a register, indicated among by the register address at the top of said FIFO queues, to the second device; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided; said data provision circuit further performing a parallel to serial conversion of said data; and a time multiplexed serial link connected to the second device, said time multiplexed serial link having a plurality of time slots, one of said time slots being a designated time slot to receive data from said plurality of registers; and said data provision circuit performing said parallel to serial conversion during said designated time slot of said time multiplexed serial link.
Claim 3
Dependent Claim
406 words
A computer system comprising: a microprocessor for performing data write operations to particular register addresses; a parallel bus coupled to said microprocessor for transferring said data and addresses of said write operations; a device for receiving data provided by said microprocessor during write operations; a communications link coupled to said device for transferring data of said operations to said device; a data transfer circuit, said data transfer circuit including: a plurality of registers addressable by said microprocessor for storing data to be transferred from said microprocessor to said device; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation detection circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; and a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from a register, indicated by the address at the top of said FIFO queue to said device; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided; said data provision circuit further performing a parallel to serial conversion of said data; and said communications link comprising a time multiplexed serial link connecting said data transfer circuit to said device, and for transferring said data write operations to said device, said time multiplexed serial link having a plurality of time slots, one of said time slots being a designated time slot to receive data from said plurality of registers; and said data provision circuit performing said parallel to serial conversion during said designated time slot of said time multiplexed serial link.
Claim 4
Dependent Claim
406 words
A computer system comprising: a microprocessor for performing data write operations to particular register addresses; a parallel bus coupled to said microprocessor for transferring said data and addresses of said write operations; a device for receiving data provided by said microprocessor during write operations; a communications link coupled to said device for transferring data of said operations to said device; a data transfer circuit, said data transfer circuit including: a plurality of registers addressable by said microprocessor for storing data to be transferred from said microprocessor to said device; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation detection circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; and a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from a register, indicated by the address at the top of said FIFO queue to said device; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided; said data provision circuit further performing a parallel to serial conversion of said data; and said communications link comprising a time multiplexed serial link connecting said data transfer circuit to said device, and for transferring said data write operations to said device, said time multiplexed serial link having a plurality of time slots, one of said time slots being a designated time slot to receive data from said plurality of registers; and said data provision circuit performing said parallel to serial conversion during said designated time slot of said time multiplexed serial link.
Claim 5
Dependent Claim
372 words
A computer system comprising: a microprocessor for performing data write operations to particular register addresses; a parallel bus coupled to said microprocessor for transferring said data and addresses of said write operations; a CODEC for receiving data provided by said microprocessor during write operations; a communications link coupled to said CODEC for transferring said data of said write operations to said CODEC; a data transfer circuit, said data transfer circuit including: a plurality of registers addressable by said microprocessor for storing data to be transferred from said microprocessor to said CODEC; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; and a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from the register, indicated by the address at the top of said FIFO queue, to said CODEC; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided; said CODEC including a plurality of registers corresponding to said plurality of registers in said data transfer circuit; the data in said plurality of registers in said transfer circuit controlling operation of said CODEC; and said communications link further transferring the address of said register containing said data of said write operations to said CODEC from said microprocessor.
Claim 6
Dependent Claim
372 words
A computer system comprising: a microprocessor for performing data write operations to particular register addresses; a parallel bus coupled to said microprocessor for transferring said data and addresses of said write operations; a CODEC for receiving data provided by said microprocessor during write operations; a communications link coupled to said CODEC for transferring said data of said write operations to said CODEC; a data transfer circuit, said data transfer circuit including: a plurality of registers addressable by said microprocessor for storing data to be transferred from said microprocessor to said CODEC; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; and a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from the register, indicated by the address at the top of said FIFO queue, to said CODEC; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided; said CODEC including a plurality of registers corresponding to said plurality of registers in said data transfer circuit; the data in said plurality of registers in said transfer circuit controlling operation of said CODEC; and said communications link further transferring the address of said register containing said data of said write operations to said CODEC from said microprocessor.
Claim 7
Dependent Claim
66 words
The computer system of claim 3, wherein certain of said plurality of registers in said device can be write protected, wherein said microprocessor can write data removing said write protection on any write operation to said plurality of registers in said data transfer circuit and wherein said write protection removal data is provided in the proper time frame with respect to addresses in said FIFO queue.
Claim 8
Dependent Claim
321 words
A computer system comprising: a microprocessor for performing data write operations to particular register addresses; a parallel bus coupled to said microprocessor for transferring said data and addresses of said write operations; a CODEC for receiving data provided by said microprocessor during write operations; a communications link coupled to said CODEC for transferring said data of said write operations to said device; and a data transfer circuit, said data transfer circuit including: a plurality of registers addressable by said microprocessor for storing data to be transferred from said microprocessor to said CODEC to control operation of said CODEC; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation detection circuit storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; and a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from the register, indicated by the address at the top of said FIFO queue, to said device; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided.
Claim 9
Dependent Claim
321 words
A computer system comprising: a microprocessor for performing data write operations to particular register addresses; a parallel bus coupled to said microprocessor for transferring said data and addresses of said write operations; a CODEC for receiving data provided by said microprocessor during write operations; a communications link coupled to said CODEC for transferring said data of said write operations to said device; and a data transfer circuit, said data transfer circuit including: a plurality of registers addressable by said microprocessor for storing data to be transferred from said microprocessor to said CODEC to control operation of said CODEC; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation detection circuit storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; and a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from the register, indicated by the address at the top of said FIFO queue, to said device; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided.
Claim 10
Independent Claim
281 words
A method for transferring data by a time multiplexed serial link from a first device to a second device using a FIFO queue for storing addresses of a plurality of registers addressable by the first device, wherein the first device performs a write operation to one of the plurality of registers, the plurality of registers storing data to be transferred from the first device to the second device, the method comprising the steps of: detecting a write operation from the first device to one of the plurality of registers; storing the data of said write operation to said one of the plurality of registers; determining if the address of said one of the plurality of registers is stored in the FIFO queue; adding the address of said one of the plurality of registers to the FIFO queue if said address is not stored in the FIFO queue when said write operation is detected; not adding the address of said one of the plurality of registers to the FIFO queue if said address is stored in the FIFO queue when said write operation is detected; and providing the data from the register of the plurality of registers indicated by the address at the top of the FIFO queue to the second device and shifting said addresses stored in the FIFO queue when said data is provided; performing parallel to serial conversion of said data during said step of providing it; wherein the time multiplexed serial link has a plurality of time slots, one of said time slots designated to receive data from said plurality of registers and wherein said step of performing parallel to serial conversion occurs during said designated time slot.
Claim 11
Independent Claim
281 words
A method for transferring data by a time multiplexed serial link from a first device to a second device using a FIFO queue for storing addresses of a plurality of registers addressable by the first device, wherein the first device performs a write operation to one of the plurality of registers, the plurality of registers storing data to be transferred from the first device to the second device, the method comprising the steps of: detecting a write operation from the first device to one of the plurality of registers; storing the data of said write operation to said one of the plurality of registers; determining if the address of said one of the plurality of registers is stored in the FIFO queue; adding the address of said one of the plurality of registers to the FIFO queue if said address is not stored in the FIFO queue when said write operation is detected; not adding the address of said one of the plurality of registers to the FIFO queue if said address is stored in the FIFO queue when said write operation is detected; and providing the data from the register of the plurality of registers indicated by the address at the top of the FIFO queue to the second device and shifting said addresses stored in the FIFO queue when said data is provided; performing parallel to serial conversion of said data during said step of providing it; wherein the time multiplexed serial link has a plurality of time slots, one of said time slots designated to receive data from said plurality of registers and wherein said step of performing parallel to serial conversion occurs during said designated time slot.
Claim 12
Dependent Claim
39 words
The method of claim 6, wherein the second device includes a plurality of registers corresponding to the plurality of registers written to by the first device and wherein said communications link further transfers the address of said one register.
Claim 13
Dependent Claim
25 words
The method of claim 7, wherein the second device is a CODEC and the data in the plurality of registers controls operation of said CODEC.
Claim 14
Dependent Claim
278 words
A circuit for transferring data from a first device to a CODEC, wherein the first device performs a write operation to transfer data, the circuit comprising: a plurality of registers addressable by the first device for storing data to be transferred from the first device to the CODEC to control the operation of the CODEC; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from a register, indicated by the register address at the top of said FIFO queue, to the CODEC; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided.
Claim 15
Dependent Claim
278 words
A circuit for transferring data from a first device to a CODEC, wherein the first device performs a write operation to transfer data, the circuit comprising: a plurality of registers addressable by the first device for storing data to be transferred from the first device to the CODEC to control the operation of the CODEC; a write operation detection circuit detecting a write operation to one of said plurality of registers; a storage response circuit operable in response to said write operation circuit and storing the data of a detected write operation to said one of said plurality of registers; a FIFO queue for storing addresses of said plurality of registers; an address determination circuit coupled to said FIFO queue for determining if the address of one of said plurality of registers is stored in said FIFO queue; an address addition circuit responsive to said address determination circuit and said write operation detection circuit, said address addition circuit adding the address of said one of said plurality of registers to said FIFO queue if said address is not stored in said FIFO queue when said write operation is detected, and not adding the address of said one of said plurality of registers to said FIFO queue if said address is stored in said FIFO queue when said write operation is detected; a data provision circuit coupled to said plurality of registers and said FIFO queue; said data provision circuit providing the data from a register, indicated by the register address at the top of said FIFO queue, to the CODEC; said data provision circuit also shifting said addresses stored in said FIFO queue when said data is provided.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |