System architecture for processing and transporting page-map or bit-map data to a raster print engine

Claim 3

The apparatus of claim 1, further comprising: passing means, initiated by said central processing unit, for transferring an image data block between said dynamic band RAM and said serial access memory.

Claim 4

The apparatus of claim 2, further comprising: a memory device for storing a multitude of image data blocks; and loading means, initiated by said CPU, for transferring an image data block from said memory device to said serial access memory; wherein said mapping means and said loading means are performed in parallel.

Claim 5

The apparatus of claim 3, further comprising: storing means for transferring an image data block from said serial access memory to said memory device; wherein said mapping means and said storing means are performed in parallel.

Claim 6

The apparatus of claim 4, wherein said dispatch means is further configured to transfer an image data block from said memory device to the raster printer.

Claim 7

The apparatus of claim 5, wherein said dispatching means includes: a FIFO buffer coupled between said serial access memory and the raster printer; and a serial bus coupled between said serial access memory and said FIFO buffer; said memory device being coupled to said serial bus.

Claim 8

The apparatus of claim 6, wherein said mapping means includes an arithmetic logic unit and a CPU data bus, said CPU data bus being coupled between said central processing unit and said dynamic band RAM, and said arithmetic logic unit being coupled to said CPU data bus.

Claim 9

The apparatus of claim 7, further comprising a SAM controller for controlling said dispatching means and said storing means, wherein said SAM controller receives dispatching commands and storing commands from said central processing unit.

Claim 10

The apparatus of claim 8, further comprising an ALU controller for controlling said mapping means, wherein said ALU controller receives mapping commands from said central processing unit.

Claim 11

A controller for processing raster page-map data for transmission to a marking engine, the page-map data being broken up into a plurality of non-overlapping, contiguous raster image data blocks, the apparatus comprising: a central processing unit; at least one video RAM device, each video RAM device including a dynamic band RAM, a serial access memory, a random access port for transmitting and receiving image data blocks to and from said dynamic band RAM, and a serial port for transmitting and receiving image data blocks to and from said serial access memory; a CPU data bus coupled between said central processing unit and said random access port, for providing access to said dynamic band RAM by said central processing unit; a dispatch FIFO coupled to the marking engine for transmitting the image data blocks to the marking engine; and a serial bus connected between said dispatch FIFO and said serial port; said video RAM devices transfer image data blocks bi-directionally between said dynamic band RAM and said serial access memory; and said video RAM devices simultaneously transfer image data blocks both to and from said serial port and to and from said random access port; whereby the controller allows transferring of image data blocks from said serial access memory to said dispatch FIFO, while simultaneously allowing access to image data blocks in said dynamic band RAM by said central processing unit.

Claim 12

A controller for processing raster page-map data for transmission to a marking engine, the page-map data being broken up into a plurality of non-overlapping, contiguous raster image data blocks, the apparatus comprising: a central processing unit; at least one video RAM device, each video RAM device including a dynamic band RAM, a serial access memory, a random access port for transmitting and receiving image data blocks to and from said dynamic band RAM, and a serial port for transmitting and receiving image data blocks to and from said serial access memory; a CPU data bus coupled between said central processing unit and said random access port, for providing access to said dynamic band RAM by said central processing unit; a dispatch FIFO coupled to the marking engine for transmitting the image data blocks to the marking engine; and a serial bus connected between said dispatch FIFO and said serial port; said video RAM devices transfer image data blocks bi-directionally between said dynamic band RAM and said serial access memory; and said video RAM devices simultaneously transfer image data blocks both to and from said serial port and to and from said random access port; whereby the controller allows transferring of image data blocks from said serial access memory to said dispatch FIFO, while simultaneously allowing access to image data blocks in said dynamic band RAM by said central processing unit.

Claim 13

The controller of claim 10, further comprising an arithmetic logic unit coupled to said CPU data bus, said arithmetic logic unit configured to perform logical operations on the image data blocks in said dynamic band RAM upon initiation by said central processing unit.

Claim 14

The controller of claim 10, further comprising: a memory device coupled to said serial bus, said memory device sized for the storage of a multitude of image data blocks; whereby the controller is further capable of transferring image data blocks from said memory device to said dispatch FIFO, while simultaneously allowing access to image data blocks in dynamic band RAM by said central processing unit; and whereby the controller is further capable of transferring image data blocks from said serial access memory to said memory device, while simultaneously allowing access to image data blocks in said dynamic band RAM by said central processing unit.

Claim 17

The apparatus of claim 13, wherein said translation look aside buffer generates a memory fault when said translation look aside buffer cannot translate a logical address to an image data block in said memory device, sent by said central processing unit, into a physical address in said dynamic band RAM.

Claim 18

A controller for processing raster page-map data for transmission to a marking engine, the page-map data being broken up into a plurality of non-overlapping, contiguous raster image data blocks, the controller comprising: a central processing unit; at least one video RAM device including a dynamic band RAM, a serial access memory, a random access port for transmitting and receiving image data blocks to and from said dynamic band RAM, and a serial port for transmitting and receiving image data blocks to and from said serial access memory; a CPU data bus coupled between said central processing unit and said random access port, for providing access to said dynamic band RAM by said central processing unit; a dispatch FIFO coupled to the marking engine for transmitting the image data blocks to the marking engine; a serial bus connected between said dispatch FIFO and said serial port; a mass memory device coupled to said serial bus, said mass memory device sized for the storage of a multitude of image data blocks; and a translation look aside buffer, said translation look aside buffer translates logical addresses to said mass memory device generated by said central processing unit into physical addresses to said dynamic band RAM; said video RAM devices transfer image data blocks bi-directionally between said dynamic band RAM and said serial access memory; and said video RAM devices simultaneously transfer image data blocks to and from said serial port and to and from said random access port; whereby the controller allows dispatching of image data blocks from said serial access memory, while simultaneously allowing mapping of image data blocks in said dynamic band RAM; whereby the controller is further capable of dispatching image data blocks from said mass memory device, while simultaneously mapping image data blocks in dynamic band RAM; whereby the controller is further capable of storing image data blocks from said serial access memory to said mass memory device, while simultaneously mapping image data blocks in said dynamic band RAM; and whereby said central processing unit provides addresses to said mass memory device and said translation look aside buffer performs actual physical addressing operations.

Claim 19

A controller for processing raster page-map data for transmission to a marking engine, the page-map data being broken up into a plurality of non-overlapping, contiguous raster image data blocks, the controller comprising: a central processing unit; at least one video RAM device including a dynamic band RAM, a serial access memory, a random access port for transmitting and receiving image data blocks to and from said dynamic band RAM, and a serial port for transmitting and receiving image data blocks to and from said serial access memory; a CPU data bus coupled between said central processing unit and said random access port, for providing access to said dynamic band RAM by said central processing unit; a dispatch FIFO coupled to the marking engine for transmitting the image data blocks to the marking engine; a serial bus connected between said dispatch FIFO and said serial port; a mass memory device coupled to said serial bus, said mass memory device sized for the storage of a multitude of image data blocks; and a translation look aside buffer, said translation look aside buffer translates logical addresses to said mass memory device generated by said central processing unit into physical addresses to said dynamic band RAM; said video RAM devices transfer image data blocks bi-directionally between said dynamic band RAM and said serial access memory; and said video RAM devices simultaneously transfer image data blocks to and from said serial port and to and from said random access port; whereby the controller allows dispatching of image data blocks from said serial access memory, while simultaneously allowing mapping of image data blocks in said dynamic band RAM; whereby the controller is further capable of dispatching image data blocks from said mass memory device, while simultaneously mapping image data blocks in dynamic band RAM; whereby the controller is further capable of storing image data blocks from said serial access memory to said mass memory device, while simultaneously mapping image data blocks in said dynamic band RAM; and whereby said central processing unit provides addresses to said mass memory device and said translation look aside buffer performs actual physical addressing operations.

Claim 20

The controller of claim 15, wherein said translation look aside buffer contains a first physical address translation corresponding to a first logical address to an image data block which has been loaded from said memory device into said dynamic band RAM.

Claim 21

The controller of claim 16, wherein said translation look aside buffer generates a memory fault when said central processing unit generates a logical address to a second image data block address of which said translation look aside buffer does not contain a second physical address translation.

Claim 22

The controller of claim 17, further comprising a means for loading said second image data block from said memory device to said dynamic band RAM in response to said memory fault.

Claim 23

The controller of claim 18, further comprising an arithmetic logic unit coupled to said CPU data bus, said logic unit, upon initiation by said central processing unit, performs logical operations on the image data blocks in said dynamic band RAM.

Claim 24

A controller for processing raster page-map data for transmission to a marking engine, the page-map data being broken up into a plurality of non-overlapping, contiguous raster image data blocks, the controller comprising: a dynamic band RAM; a memory device coupled to said dynamic band RAM by a data bus; a central processing unit for mapping image data blocks in said dynamic band RAM, said central processing unit addressing an image data block by generating a logical address to said memory device; and a translation look aside buffer configured to translate said logical address generated by said central processing unit into a physical address to said dynamic band RAM.

Claim 25

A controller for processing raster page-map data for transmission to a marking engine, the page-map data being broken up into a plurality of non-overlapping, contiguous raster image data blocks, the controller comprising: a dynamic band RAM; a memory device coupled to said dynamic band RAM by a data bus; a central processing unit for mapping image data blocks in said dynamic band RAM, said central processing unit addressing an image data block by generating a logical address to said memory device; and a translation look aside buffer configured to translate said logical address generated by said central processing unit into a physical address to said dynamic band RAM.