US5420696A
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US
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Image data transfer architecture and method for an electronic reprographic machine
Assignee: Xerox Corp
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Filing: 1993-06-24
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Granted: 1995-05-30
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Expires: 2013-06-24
Abstract
Abstract An image data transfer architecture in which control data and image data are isolated is provided. Bidirectional buffers isolate data buses from the control bus, thereby allowing control to be maintained by an 8-bit programmed microprocessor. The controller microprocessor does not handle image data thereby reducing complex software and support components required of prior multiple 16- and 32-bit microprocessor controller systems. Isolation is achieved by having multiple data buses handling image data at various stages of processing, such as, for example, input image data, compressed image data and output image data. Additional efficiencies are realized by eliminating the inherent delays caused when high speed image output terminals are forced to share data buses with much lower speed image input terminals.
Inventors
- 👤 Donald L. Wegeng
- 👤 Jeff C. Carter
- 👤 Joseph W. Ward
- 👤 Thomas G. Beaman
- 👤 Gregory C. Sosinski
- 👤 Todd M. Austin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:58
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/32; H04N1/32561; H04N1/32598; H04N1/32603; H04N1/00127; H04N1/00204; H04N2201/00; H04N2201/0077; H04N2201/0081; H04N2201/0082; H04N2201/0087
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
276 words
An image data transfer architecture, comprising: a bus and data transfer controller; a control bus transmitting control signals generated by said controller; a plurality of data buses transmitting data according to control signals generated by said controller; a plurality of bidirectional data buffers in selective communication with said plurality of data buses, said buffers isolating said plurality of buses during a data transfer operation; a plurality of direct memory access controllers in selective communication with said plurality of data buses, said direct memory access controllers controlling data transfers between a plurality of data handling devices and said plurality of data buses; an input buffer in selective communication with at least one of said plurality of data buses, said input buffer temporarily storing a bitmapped image generated by an image input terminal; a data compressor in selective communication with said at least one of said plurality of data buses, said data compressor compressing said bitmapped image to form a compressed bitmapped image; a data storage device in selective communication with said at least one of said plurality of data buses, said data storage device storing said compressed bitmapped image; a data decompressor in selective communication with said at least one of said plurality of data buses, said data decompressor receiving said compressed bitmapped image data from said data storage device via at least one of said plurality of data buses and decompressing said compressed bitmapped image to reform said bitmapped image; and at least one output buffer in selective communication with at least one of said plurality of data buses to temporarily store said bitmapped image prior to transmission of said bitmapped image to an output device.
Claim 2
Dependent Claim
276 words
An image data transfer architecture, comprising: a bus and data transfer controller; a control bus transmitting control signals generated by said controller; a plurality of data buses transmitting data according to control signals generated by said controller; a plurality of bidirectional data buffers in selective communication with said plurality of data buses, said buffers isolating said plurality of buses during a data transfer operation; a plurality of direct memory access controllers in selective communication with said plurality of data buses, said direct memory access controllers controlling data transfers between a plurality of data handling devices and said plurality of data buses; an input buffer in selective communication with at least one of said plurality of data buses, said input buffer temporarily storing a bitmapped image generated by an image input terminal; a data compressor in selective communication with said at least one of said plurality of data buses, said data compressor compressing said bitmapped image to form a compressed bitmapped image; a data storage device in selective communication with said at least one of said plurality of data buses, said data storage device storing said compressed bitmapped image; a data decompressor in selective communication with said at least one of said plurality of data buses, said data decompressor receiving said compressed bitmapped image data from said data storage device via at least one of said plurality of data buses and decompressing said compressed bitmapped image to reform said bitmapped image; and at least one output buffer in selective communication with at least one of said plurality of data buses to temporarily store said bitmapped image prior to transmission of said bitmapped image to an output device.
Claim 3
Dependent Claim
19 words
The image data transfer architecture of claim 1, wherein said bus and data transfer controller is a programmed microprocessor.
Claim 4
Dependent Claim
17 words
The image data transfer architecture of claim 2, wherein said programmed microprocessor is an eight-bit programmed microprocessor.
Claim 5
Dependent Claim
42 words
The image data transfer architecture of claim 1, further comprising: a floppy disk drive in selective communication with at least one of said plurality of data buses, said floppy disk drive providing character image data directly to said image data transfer architecture.
Claim 6
Dependent Claim
48 words
The image data transfer architecture of claim 1, further comprising: a personal computer interface in selective communication with at least one of said plurality of data buses, said personal computer interface providing character and bitmapped image data directly to said image data transfer architecture from a personal computer.
Claim 7
Dependent Claim
39 words
The image data transfer architecture of claim 5, wherein said character and bitmapped image data provided directly by said personal computer is merged with an existing image scanned into the image data transfer architecture via said image input terminal.
Claim 8
Dependent Claim
32 words
The image data transfer architecture of claim 4, further comprising: a character generator in selective communication with said floppy disk, said character generator providing said character image data to said output buffers.
Claim 9
Dependent Claim
36 words
The image data transfer architecture of claim 7, wherein said character image data provided by said character generator is merged with an existing image scanned into the image data transfer architecture via said image input terminal.
Claim 10
Dependent Claim
130 words
The image data transfer architecture of claim 1, wherein said plurality of data buses comprise: a control bus providing control signals from said controller to said plurality of data handling devices; an input bus providing transmission of image data between data handling devices, including said input buffer, said data compressor, said data storage device and at least one of said plurality of direct memory access controllers; a decompression bus providing transmission of compressed bitmapped image data between said input bus, said data storage device, said data decompressor and at least one of said plurality of direct memory access controllers; and an output bus providing transmission of decompressed image data, said at least one output buffer, a character generator and at least one of said plurality of direct memory access controllers.
Claim 11
Dependent Claim
222 words
An image data transfer apparatus, comprising: controller means for controlling a plurality of data transfer buses and a plurality of data handling devices; a plurality of buses for transferring data and control signals according to various signals initiated by said controller means; a plurality of bidirectional data buffers selectively connected to said plurality of buses for isolating said plurality of buses from one another in accordance with signals received from said controller means; a plurality of direct memory access controllers for controlling data transfers between said plurality of data handling devices via said plurality of buses; an input buffer selectively connected to at least one of said plurality of buses for receiving bitmapped image data from an image input means; data compression means selectively connected to at least one of said plurality of buses for compressing said bitmapped image data to form a compressed bitmapped image; data storage means for storing said compressed bitmapped image; data decompression means for decompressing said compressed bitmapped image received from said data storage means via at least one of said plurality of buses to reform said bitmapped image; at least one output buffer for temporarily storing said bitmapped image received from said data decompression means via at least one of said plurality of buses prior to transmission of said bitmapped image to an image output means.
Claim 12
Dependent Claim
222 words
An image data transfer apparatus, comprising: controller means for controlling a plurality of data transfer buses and a plurality of data handling devices; a plurality of buses for transferring data and control signals according to various signals initiated by said controller means; a plurality of bidirectional data buffers selectively connected to said plurality of buses for isolating said plurality of buses from one another in accordance with signals received from said controller means; a plurality of direct memory access controllers for controlling data transfers between said plurality of data handling devices via said plurality of buses; an input buffer selectively connected to at least one of said plurality of buses for receiving bitmapped image data from an image input means; data compression means selectively connected to at least one of said plurality of buses for compressing said bitmapped image data to form a compressed bitmapped image; data storage means for storing said compressed bitmapped image; data decompression means for decompressing said compressed bitmapped image received from said data storage means via at least one of said plurality of buses to reform said bitmapped image; at least one output buffer for temporarily storing said bitmapped image received from said data decompression means via at least one of said plurality of buses prior to transmission of said bitmapped image to an image output means.
Claim 13
Dependent Claim
16 words
The image data transfer apparatus of claim 10, wherein said controller means is a programmed microprocessor.
Claim 14
Dependent Claim
15 words
The image data transfer apparatus of claim 11, wherein said microprocessor is an eight-bit microprocessor.
Claim 15
Dependent Claim
35 words
The image data transfer apparatus of claim 10, further comprising: a floppy disk drive selectively connected to at least one of said plurality of buses for providing character image data to said image output means.
Claim 16
Dependent Claim
48 words
The image data transfer apparatus of claim 10, further comprising: a personal computer interface means for providing a direct connection between said image data transfer apparatus and a personal computer, said personal computer directly providing bitmapped image data and character image data to said image data transfer apparatus.
Claim 17
Dependent Claim
30 words
The image transfer apparatus of claim 13, further comprising: a character generator in selective communication with said floppy disk, said character generator providing character image data to said output buffers.
Claim 18
Dependent Claim
36 words
The image data transfer apparatus of claim 15, wherein said character image data provided by said character generator is merged with an existing image scanned into the image data transfer apparatus via said image input means.
Claim 19
Dependent Claim
38 words
The image data transfer apparatus of claim 14, wherein said character and bitmapped image data provided by said personal computer is merged with an existing image scanned into the image data transfer apparatus via said image input means.
Claim 20
Dependent Claim
146 words
The image data transfer apparatus of claim 10, wherein said plurality of buses comprise: a control bus for transmitting control signals from said control means to said data handling devices, said bidirectional buffers, said direct memory access controllers and said data storage device; an input data bus for receiving bitmapped image data from said image input means and transmitting said bitmapped image between said input buffer and said data compression means and between said data compression means and said data storage means; a decompression bus for transferring said compressed bitmapped image data from said data storage means to said decompression means; and an output data bus for receiving said bitmapped image data from said decompression means and transmitting said bitmapped image data to said at least one output buffer and transmitting said bitmapped data from said at least one output buffer to said image output means.
Claim 21
Dependent Claim
250 words
An image data transfer architecture, comprising: a control bus operatively connected to a programmed microprocessor controller, a floppy disk, a first, second and third direct memory access controller, a first, second and third bidirectional buffer, a character generator and at least one output controller, wherein said control bus transmits control signals generated by said microprocessor controller to control data traffic on a plurality of buses and said control bus providing data transmission capability between said floppy disk and said character generator; an input bus operatively connected to said floppy disk, said first direct memory access controller, said first bidirectional buffer, an input buffer, a data compressor, a personal computer interface and a data storage device, wherein said input bus transmits bitmapped image data from an image input device to the input buffer and from the input buffer to the data compressor and a compressed bitmapped image from the data compressor to the data storage device; a decompression bus operatively connected to said data storage device, said second direct memory access controller, said second bidirectional buffer and a data decompressor, wherein said decompression bus transmits compressed bitmapped image data from said data storage device to said data decompressor; and an output bus operatively connected to said data decompressor, said third direct memory access controller, said third bidirectional buffer, said character generator and said at least one output buffer, wherein said output bus transmits bitmapped image data from said data decompressor and said character generator to said at least one output buffer.
Claim 22
Dependent Claim
250 words
An image data transfer architecture, comprising: a control bus operatively connected to a programmed microprocessor controller, a floppy disk, a first, second and third direct memory access controller, a first, second and third bidirectional buffer, a character generator and at least one output controller, wherein said control bus transmits control signals generated by said microprocessor controller to control data traffic on a plurality of buses and said control bus providing data transmission capability between said floppy disk and said character generator; an input bus operatively connected to said floppy disk, said first direct memory access controller, said first bidirectional buffer, an input buffer, a data compressor, a personal computer interface and a data storage device, wherein said input bus transmits bitmapped image data from an image input device to the input buffer and from the input buffer to the data compressor and a compressed bitmapped image from the data compressor to the data storage device; a decompression bus operatively connected to said data storage device, said second direct memory access controller, said second bidirectional buffer and a data decompressor, wherein said decompression bus transmits compressed bitmapped image data from said data storage device to said data decompressor; and an output bus operatively connected to said data decompressor, said third direct memory access controller, said third bidirectional buffer, said character generator and said at least one output buffer, wherein said output bus transmits bitmapped image data from said data decompressor and said character generator to said at least one output buffer.
Claim 23
Dependent Claim
26 words
The image data transfer architecture of claim 19, wherein the image input device is at least one of a personal computer and an image input terminal.
Claim 24
Dependent Claim
18 words
The image data transfer architecture of claim 20, wherein the image input terminal is a raster input scanner.
Claim 25
Dependent Claim
16 words
The image data transfer architecture of claim 19, wherein the programmed microprocessor is an eight-bit microprocessor.
Claim 26
Dependent Claim
22 words
The image data transfer architecture of claim 19, wherein the character generator convert ASCII data to character image data to be output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-29 | 1998-11-28 | 1999-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-29 | 2002-11-28 | 2003-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-29 | 2006-11-28 | 2007-05-30 | $7700.00 | Window Closed / Lapsed |