Apparatus for assembling data for supply to a scanning output device

Claim 3

The apparatus of claim 12, wherein the image data interface means includes: source interface means, adapted for communication with the source memory and coupled to the control means and the address generating means, for reading and writing image data words in the source memory in response to transaction control signals and source addresses; assembly interface means, adapted for communication with the assembly memory and coupled to the control means, the address generating means and the source interface means, for assembling image data words in the assembly memory and for reading assembled data in the assembly memory in response to transaction control signals and assembly addresses.

Claim 4

The apparatus of claim 2, wherein the control means includes: mode control means, connected to the storage means and responsive to a control word stored in the storage means that indicates a selected mode of operation for the apparatus, for generating transaction type signals to implement the selected mode; scan control means, connected to the storage means and the scanner interface means and responsive to communication with the scanner interface means and control words stored in the storage means, for generating transaction type signals to maintain the supply of assembled data words to the scanning device; transaction type selecting means, connected to the mode control means and the scan control means, for selecting a transaction type signal from the scan control means or the mode control means; and transaction control means, connected to the transaction type selecting means, the address generating means, the assembly interface means, the source interface means and the storage means and responsive to the selected transaction type signal, for generating the transaction control signals.

Claim 5

The apparatus of claim 3, wherein the assembly memory includes a buffer address space including a first band and a second band, and the control means further includes: band control means, connected to the scan control means, the mode control means and the transaction control means, for coordinating access to the first band and the second band so that one band may be accessed by the assembly interface means for supply of data to the scanner interface means and the other band may be accessed in a multiplexed manner by the assembly interface means for writing data from the source interface means.

Claim 6

The apparatus of claim 4, wherein the memory storage location identified by the destination address in the destination command word is addressable by a number of assembly addresses that correspond to the size of the source image block, and wherein the first one of said plurality of assembly addresses resides in one of the first and second bands and the remaining ones of the plurality of assembly addresses reside in the other of the first and second bands, and wherein the control means further includes: means, in communication with the control interface means and the address generating means, for generating an interrupt when an assembly address is generated by the address generating means that resides outside the one band in which the first assembly address of the plurality resided.

Claim 7

The apparatus of claim 5, wherein the control means further includes: means for writing parameters indicating the nature of the interrupt to the storage means, whereby the processor may access the parameters through the control interface means.

Claim 8

The apparatus of claim 1, wherein the control words further include a control command word, a source command word and a destination command word and wherein: the control means is responsive to the control command word in generating transaction control signals.

Claim 9

The apparatus of claim 1, wherein the source command word further includes data indicating the size of the source image block, and the address generating means generates a plurality of source addresses in response to the source address of the image block and its size.

Claim 10

The apparatus of claim 1, wherein the source command word further includes data indicating the size of the source image block, and the address generating means generates a plurality of assembly addresses in response to the destination virtual address of the image block and its size.

Claim 11

The apparatus of claim 1, wherein one of the plurality of modes of operation is a font load mode, and the control words include a destination command word including a destination address of a font memory storage location, a font memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the font load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the source address indicated by the destination

Claim 12

The apparatus of claim 10, wherein the address generating means generates a plurality of source addresses in the font load mode, one in response to each image data word of the image block written to the control interface means by the processor.

Claim 13

The apparatus of claim 1, wherein one of the plurality of modes of operation is a source load mode; and the control words include a destination command word including a destination address of a source memory storage location in the source load mode, a source memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the source load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the source address.

Claim 14

The apparatus of claim 12, wherein the address generating means generates a plurality of source addresses in the source load mode, one in response to each image data word of the image block written to the control interface means by the processor.

Claim 15

The apparatus of claim 1, wherein one of he plurality of modes of operation is graphics load mode; and the control words include a destination command word including a destination address of a graphics memory storage location for a graphics load mode, a graphics memory storage location including data locations addressable by assembly addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the graphics load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the assembly address.

Claim 16

The apparatus of claim 14, wherein the source command word in the graphics load mode includes data indicating the number of image data words per line in the graphics image block, and the address generating means generates a plurality of assembly addresses in the graphics load mode in response to the destination address and the number of image data words per line in the graphics image block.

Claim 17

The apparatus of claim 1, wherein one of the plurality of modes of operation is a source read mode; and the control words include a destination command word including a source address of a source memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the source read mode so that the image data interface means reads a data word from the source memory storage location and transfers the data word to the control interface means.

Claim 18

The apparatus of claim 16, wherein the address generating means generates a plurality of source addresses in the source read mode, one in response to each read by the processor to the control interface means.

Claim 19

The apparatus of claim 1, wherein the source command word further includes a texture command word including a source address of a texture image block, a texture image block including one or more texture data words, the apparatus further including: combining means, in communication with the control means, and the image data interface means, for combining image data words and texture data words to generate textured data words; and wherein the control means is responsive to the control command word to generate transaction control signals in the dispatch mode so that the image data interface means reads the image data word and the texture data word in the respective source addresses and transfers the image data word and texture data word to the combining means, the combining means combines the image data word and the texture data word to generate a textured data word, and the image data interface means stores the textured data word in the assembly address.

Claim 20

The apparatus of claim 1, wherein the destination command word, further includes an offset defining a bit alignment within the memory storage location, the apparatus further including: aligning means, in communication with the storage means, the control means, and the image data interface means, for aligning image data words on bit boundaries in response to the offset; and wherein the control means is responsive to the control command word to generate transaction control signals in the dispatch mode so that the image data interface means reads the image data word in the source address and transfers the image data word to the aligning means, the aligning means aligns the image data word to generate an aligned image data word, and the image data interface means stores the aligned image data word in the assembly address.

Claim 21

An integrated circuit for assembling image data words for supply to a raster printer under control of a processor that generates control words, image data words being stored in a source memory accessible in response to source addresses and image data words being assembled in an assembly memory accessible in response to assembly addresses, the control words including a code indicating one of a plurality of modes of operation, a code identifying a source address of an image block including one or more image data words and a code indicating a destination address of a memory storage location in the assembly memory at which the source image block is to be stored, the control words further including a code indicating a source address of a texture image block including one or more data words, said integrated circuit comprising: a control interface means, adapted for communication with the processor, for receiving the control words; storage means, in communication with the control interface means, for storing and outputting the control words; control means, in communication with the control interface means and the storage means, for generating transaction control signals in response to the control words; address generating means, in communication with the storage means and the control means, for generating the source addresses and the assembly addresses in response to the transaction control signals and the codes indicating the source address of the image data block and the destination address of the memory storage location in the assembly memory in which the image block is to be stored; image data interface means, adapted for communication with the source memory and assembly memory and coupled to the control means and the address generating means, for reading and writing image data words in the source memory and the assembly memory in response to the transaction control signals and the source addresses and assembly addresses; printer interface means, adapted for communication with the printer and coupled to the image data interface means, for supplying data words from the assembly memory through the image data interface means to the printer; and combining means, in communication with the control means and the image data interface means, for combining image data words and texture data words to generate textured data words, and wherein the control means is responsive to the control words in at least one of the plurality of modes to generate transaction control signals so that the image data interface means reads the image data word and the texture data word in the respective source addresses and transfers the image data word and texture data word to the combining means, the combining means combines the image data word and the texture data word to generate a textured data word, and the image data interface means stores the textured data word in the assembly address supplied by the address generating means.

Claim 22

An integrated circuit for assembling image data words for supply to a raster printer under control of a processor that generates control words, image data words being stored in a source memory accessible in response to source addresses and image data words being assembled in an assembly memory accessible in response to assembly addresses, the control words including a code indicating one of a plurality of modes of operation, a code identifying a source address of an image block including one or more image data words and a code indicating a destination address of a memory storage location in the assembly memory at which the source image block is to be stored, the control words further including a code indicating a source address of a texture image block including one or more data words, said integrated circuit comprising: a control interface means, adapted for communication with the processor, for receiving the control words; storage means, in communication with the control interface means, for storing and outputting the control words; control means, in communication with the control interface means and the storage means, for generating transaction control signals in response to the control words; address generating means, in communication with the storage means and the control means, for generating the source addresses and the assembly addresses in response to the transaction control signals and the codes indicating the source address of the image data block and the destination address of the memory storage location in the assembly memory in which the image block is to be stored; image data interface means, adapted for communication with the source memory and assembly memory and coupled to the control means and the address generating means, for reading and writing image data words in the source memory and the assembly memory in response to the transaction control signals and the source addresses and assembly addresses; printer interface means, adapted for communication with the printer and coupled to the image data interface means, for supplying data words from the assembly memory through the image data interface means to the printer; and combining means, in communication with the control means and the image data interface means, for combining image data words and texture data words to generate textured data words, and wherein the control means is responsive to the control words in at least one of the plurality of modes to generate transaction control signals so that the image data interface means reads the image data word and the texture data word in the respective source addresses and transfers the image data word and texture data word to the combining means, the combining means combines the image data word and the texture data word to generate a textured data word, and the image data interface means stores the textured data word in the assembly address supplied by the address generating means.

Claim 23

The integrated circuit of claim 20, wherein the image data interface means includes: a source interface means, adapted for communication with the source memory and coupled to the control means and the address generating means, for reading and writing image data words in the source image block in response to the transaction control signals and source addresses supplied by the address generating means; and assembly interface means, adapted for communication with the assembly memory and coupled to the control means, the address generating means and the source interface means, for assembling image data words in the assembly memory in response to the assembly addresses supplied by the address generating means, and for reading assembled data in the assembly memory in response to transaction control signals for supply to the printer.

Claim 24

The integrated circuit of claim 20, wherein one of the plurality of modes is the dispatch mode, and wherein: the control means is responsive to the control words to generate transaction control signals in the dispatch mode so that the image data interface means reads the image data block from the source memory in response to addresses supplied by the address generating means, and transfers the image data block to the assembly memory in response to the assembly addresses supplied by the address generating means.

Claim 25

The integrated circuit of claim 22, wherein the assembly memory includes a buffer address space including a first band and a second band, and the control means further includes: band control means, in communication with the image data interface means, for coordinating access to the first band and the second band so that one band may be accessed by the image data interface means for supply of data to the printer and the other band is accessed by the image data interface means for writing data from the source memory.

Claim 26

The integrated circuit of claim 23, wherein the memory storage location identified by the destination address is addressable by a number of assembly addresses that correspond to the size of the source image block, and wherein the first one of said plurality of assembly addresses may reside in one of the first and second bands while another one of the plurality of assembly addresses reside in the other of the first and second bands, and wherein the control means further includes: means, in communication with the control interface means and the address generating means, for generating an interrupt when an assembly address is generated by the address generating means that resides outside the one band in which the first assembly address of the plurality resides.

Claim 27

The integrated circuit of claim 24, wherein the control means further includes: means for writing parameters indicating the nature of the interrupt to the storage means, whereby the processor may access the parameters through the control interface means.

Claim 28

The integrated circuit of claim 22, wherein the source command word further includes data indicating the size of the source image block, and the address generating means generates a plurality of source addresses in response to the source address of the image block and its size.

Claim 29

The integrated circuit of claim 22, wherein the source command word further includes data indicating the size of the source image block, and the address generating means generates a plurality of assembly addresses in response to the destination address and the size of the source image block.

Claim 30

The integrated circuit of claim 20, wherein the code indicating the destination address of a memory storage location in the assembly memory includes an offset value defining bit alignment within the storage location, the integrated circuit further including: aligning means, in communication with the storage means, the control means and the image data interface means, for aligning image data words on bit boundaries in response to the offset, and wherein the control means is responsive to the control words in the dispatch mode to generate transaction control signals so that the image data interface reads the image data word and the source address supplied by the address generating means and transfers the image data word to the aligning means, the aligning means aligns the image data word to generate an aligned image data word, and the image data interface means stores the aligned image data words in the assembly address supplied by the address generating means.

Claim 31

The integrated circuit of claim 20, wherein one of the plurality of modes of operation is a font load mode, and the control words include a code identifying a destination address of a memory storage location, a memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the font load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the destination address.

Claim 32

The integrated circuit of claim 29, wherein the address generating means generates a plurality of source addresses, one in response to each image data word of an image block written to the control interface means by the processor.

Claim 33

The integrated circuit of claim 20, wherein one o the plurality of modes of operation is a source load mode; and the control words include a code indicating destination address of a memory storage location in the source load mode, a memory storage location including data locations addressable by one or more source addresses, and wherein: the control means is responsive to the control command word to generate transaction control signals in the source load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the destination address.

Claim 34

The integrated circuit of claim 31, wherein the address generating means generates a plurality of destination addresses, one in response to each image data word of an image block written by the processor to the control interface means.

Claim 35

The integrated circuit of claim 20, wherein one of the plurality of modes of operation is a graphics load mode; and the control words include a code indicating a destination address of a memory storage location for a graphics image block in the graphics load mode, a memory storage location including data locations addressable by assembly or source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the graphics load mode so that the control interface means accepts an image data word from the processor and transfers the image data word to the image data interface means, and the image data interface means writes the image data word to the destination address.

Claim 36

The integrated circuit of claim 33, wherein the control words in the graphics load mode include data indicating the number of image data words per line in the graphics image block, and the address generating means generates a plurality of assembly addresses in response to the destination address and the number of image data words per line in the graphics image block.

Claim 37

The integrated circuit of claim 20, wherein one of the plurality of modes of operation is a source read mode; and the control words include a code indicating a source address of a memory storage location including data locations addressable by one or more source addresses and wherein: the control means is responsive to the control command word to generate transaction control signals in the source read mode so that the image data interface means reads a data word from the memory storage location and transfers the data word to the control interface means.

Claim 38

The integrated circuit of claim 35, wherein the address generating means generates a plurality of source addresses, one in response to each read by the processor to the control interface means.

Claim 41

The apparatus of claim 37, wherein the control means further includes: means for writing parameters indicating the nature of the interrupt to the storage means, whereby the processor may access the parameters through the control interface means.