US5796587A
Expired / Lapsed
US
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Printed circut board with embedded decoupling capacitance and method for producing same
Assignee: GlobalFoundries Inc
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Filing: 1996-06-12
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Granted: 1998-08-18
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Expires: 2016-06-12
Abstract
Abstract A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
Inventors
- 👤 John M. Lauffer
- 👤 Konstantinos Papathomas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:28
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/16; H05K1/162; H10; H10D; H10D84/00; H05K3/00; H05K3/46; H05K3/4611; H05K3/4641; H05K2201/00; H05K2201/02; H05K2201/0203; H05K2201/0206; H05K2201/0209; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0355; H05K2201/09; H05K2201/09209; H05K2201/0929; H05K2201/09309; H05K2203/00; H05K2203/07; H05K2203/0756; H05K2203/0759; H05K3/40; H05K3/42; H05K3/429; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
69 words
An electronic circuit package comprising: a first core and a second core, each fabricated by lamination and circuitization; and one or more embedded capacitors interleaved between the first core and the second core; each embedded capacitor comprising a first conductor foil coated on at least one side with a dielectric material; and a second conductor foil on top of the coating of dielectric material on the first conductor foil.
Claim 2
Dependent Claim
69 words
An electronic circuit package comprising: a first core and a second core, each fabricated by lamination and circuitization; and one or more embedded capacitors interleaved between the first core and the second core; each embedded capacitor comprising a first conductor foil coated on at least one side with a dielectric material; and a second conductor foil on top of the coating of dielectric material on the first conductor foil.
Claim 3
Dependent Claim
23 words
The electronic circuit package of claim 1, wherein at least one side of the second conductor foil is coated with the dielectric material.
Claim 4
Dependent Claim
21 words
The electronic circuit package of claim 1, wherein both sides of the first conductor foil are coated with the dielectric material.
Claim 5
Dependent Claim
60 words
A printed circuit board comprising: a first core and a second core, each fabricated by lamination and circuitization; a first conductor foil; a second conductor foil; a dielectric material coated on at least one side of each of the first conductor foil and the second conductor foil; and a third conductor foil drilled in a ground plane clearance hole pattern.
Claim 6
Dependent Claim
60 words
A printed circuit board comprising: a first core and a second core, each fabricated by lamination and circuitization; a first conductor foil; a second conductor foil; a dielectric material coated on at least one side of each of the first conductor foil and the second conductor foil; and a third conductor foil drilled in a ground plane clearance hole pattern.
Claim 7
Dependent Claim
21 words
The printed circuit board of claim 4 wherein the first conductor foil and the second conductor foil are made of copper.
Claim 8
Dependent Claim
17 words
The printed circuit board of claim 4 wherein the drilled third conductive foil is made of copper.
Claim 9
Dependent Claim
72 words
A printed circuit board comprising: a first core and a second core, each fabricated by lamination and circuitization: a first conductor foil; a second conductor foil; a dielectric material coated on at least one side of each of the first conductor foil and the second conductor foil wherein the dielectric material is applied to a thickness of approximately 0.0015"; and a third conductor foil drilled in a ground plane clearance hole pattern.
Claim 10
Dependent Claim
72 words
A printed circuit board comprising: a first core and a second core, each fabricated by lamination and circuitization: a first conductor foil; a second conductor foil; a dielectric material coated on at least one side of each of the first conductor foil and the second conductor foil wherein the dielectric material is applied to a thickness of approximately 0.0015"; and a third conductor foil drilled in a ground plane clearance hole pattern.
Claim 11
Dependent Claim
76 words
A printed circuit board comprising: a first core and a second core, each fabricated by lamination and circuitization: a first conductor foil; a second conductor foil; a dielectric material coated on at least one side of each of the first conductor foil and the second conductor foil wherein the dielectric material is selected from the group comprising polytetrafluoroethylene, cyanate ester, BT-epoxy, and polyimide; and a third conductor foil drilled in a ground plane clearance hole pattern.
Claim 12
Dependent Claim
76 words
A printed circuit board comprising: a first core and a second core, each fabricated by lamination and circuitization: a first conductor foil; a second conductor foil; a dielectric material coated on at least one side of each of the first conductor foil and the second conductor foil wherein the dielectric material is selected from the group comprising polytetrafluoroethylene, cyanate ester, BT-epoxy, and polyimide; and a third conductor foil drilled in a ground plane clearance hole pattern.
Claim 13
Dependent Claim
81 words
An electronic circuit package comprising: a first core and a second core, each fabricated by lamination and circuitization; and one or more embedded capacitors interleaved between the first core and the second core; each embedded capacitor comprising: a first conductor foil coated on at least one side with a dielectric material; and a second conductor foil on top of the coating of dielectric material on the first conductor foil; wherein the dielectric material is applied to a thickness of approximately 0.0015".
Claim 14
Dependent Claim
81 words
An electronic circuit package comprising: a first core and a second core, each fabricated by lamination and circuitization; and one or more embedded capacitors interleaved between the first core and the second core; each embedded capacitor comprising: a first conductor foil coated on at least one side with a dielectric material; and a second conductor foil on top of the coating of dielectric material on the first conductor foil; wherein the dielectric material is applied to a thickness of approximately 0.0015".
Claim 15
Dependent Claim
85 words
An electronic circuit package comprising: a first core and a second core, each fabricated by lamination and circuitization; and one or more embedded capacitors interleaved between the first core and the second core; each embedded capacitor comprising: a first conductor foil coated on at least one side with a dielectric material; and a second conductor foil on top of the coating of dielectric material on the first conductor foil; wherein the dielectric material is selected from the group comprising polytetrafluoroethylene, cyanate ester, BT-epoxy, and polyimide.
Claim 16
Dependent Claim
85 words
An electronic circuit package comprising: a first core and a second core, each fabricated by lamination and circuitization; and one or more embedded capacitors interleaved between the first core and the second core; each embedded capacitor comprising: a first conductor foil coated on at least one side with a dielectric material; and a second conductor foil on top of the coating of dielectric material on the first conductor foil; wherein the dielectric material is selected from the group comprising polytetrafluoroethylene, cyanate ester, BT-epoxy, and polyimide.
References Cited (Backward Citations)
US4792779A
Cited
US4775573A
Cited
US5010641A
Cited
US5079069A
Cited
US5155655A
Cited
US5161086A
Cited
JPH03283592A
Cited
US5027253A
Cited
US5172304A
Cited
US5144526A
Cited
US5162977A
Cited
US5261153A
Cited
WO1994002310A1
Cited
US5428499A
Cited
US5469324A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |