Packaging and interconnect system for integrated circuits

Claim 2

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one integrated circuit die having first and second surfaces and disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said I/O connection pads electrically connected to said first bonding pads.

Claim 3

The multichip module packaging structure of claim 1 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

Claim 4

The multichip module packaging structure of claim 1 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

Claim 5

The multichip module packaging structure of claim 1 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

Claim 6

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die having first and second surfaces and disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; and at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit.

Claim 7

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die having first and second surfaces and disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; and at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit.

Claim 8

The multichip module packaging structure of claim 5 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

Claim 9

The multichip module packaging structure of claim 5 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

Claim 10

The multichip module packaging structure of claim 5 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

Claim 11

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavities formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; a plurality of integrated circuit dice having first and second surfaces, one of said integrated circuit dice disposed within each of said plurality of chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice aligned so that its plurality of I/O connection pads align with ones of first bonding pads, said I/O connection pads electrically connected to said first bonding pads.

Claim 12

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavities formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; a plurality of integrated circuit dice having first and second surfaces, one of said integrated circuit dice disposed within each of said plurality of chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice aligned so that its plurality of I/O connection pads align with ones of first bonding pads, said I/O connection pads electrically connected to said first bonding pads.

Claim 13

The multichip module packaging structure of claim 9 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

Claim 14

The multichip module packaging structure of claim 9 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

Claim 15

The multichip module packaging structure of claim 9 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

Claim 16

The multichip module packaging structure of claim 9 further including a layer of encapsulant disposed over said plurality of integrated circuit dice in said at least one chip mounting cavity.

Claim 17

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; a plurality of integrated circuit dice having first and second surfaces, one of said integrated circuit dice disposed within each of said chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said first integrated circuit dice including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice aligned so that its plurality of I/O connection pads align with ones of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; and at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit.

Claim 18

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; a plurality of integrated circuit dice having first and second surfaces, one of said integrated circuit dice disposed within each of said chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said first integrated circuit dice including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice aligned so that its plurality of I/O connection pads align with ones of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; and at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit.

Claim 19

The multichip module packaging structure of claim 14 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

Claim 20

The multichip module packaging structure of claim 14 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

Claim 21

The multichip module packaging structure of claim 14 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

Claim 22

The multichip module packaging structure of claim 14 further including a layer of encapsulant disposed over said first and second integrated circuit dice.

Claim 23

The multichip module packaging structure of claim 14 wherein said at least one second integrated circuit die comprises a plurality of integrated circuit dice.

Claim 24

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die having first and second surfaces and disposed within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; a leadframe having outer leads extending outside of a periphery of said multichip module packaging structure and having inner bond leads electrically bonded to ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit disposed about a periphery thereof; a multi-layer laminate board mechanically bonded over said second surface of said thin film multilayer interconnect circuit and over said inner bond leads of said lead frame, said multilayer laminate board having a first layer including conductive pads extending outward from about an inner periphery thereof, said multilayer laminate board further having a second layer including apertures formed therethrough, said apertures aligned with outwardly extending portions of said conductive pads and exposing an upper surface of said conductive pads.

Claim 25

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die having first and second surfaces and disposed within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; a leadframe having outer leads extending outside of a periphery of said multichip module packaging structure and having inner bond leads electrically bonded to ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit disposed about a periphery thereof; a multi-layer laminate board mechanically bonded over said second surface of said thin film multilayer interconnect circuit and over said inner bond leads of said lead frame, said multilayer laminate board having a first layer including conductive pads extending outward from about an inner periphery thereof, said multilayer laminate board further having a second layer including apertures formed therethrough, said apertures aligned with outwardly extending portions of said conductive pads and exposing an upper surface of said conductive pads.

Claim 26

The multichip module packaging structure of claim 20 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

Claim 27

The multichip module packaging structure of claim 20 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

Claim 28

The multichip module packaging structure of claim 20 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

Claim 29

The multichip module packaging structure of claim 20 further including a layer of encapsulant disposed over said at least one first and second integrated circuit die.

Claim 30

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die disposed in said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having a first surface bonded to said first surface of said thin film multilayer interconnect circuit in a position such that said plurality of first bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of first I/O connection pads wire bonded to corresponding ones of said plurality of first bonding pads of said thin film multilayer interconnect circuit; at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; and a leadframe having outer leads extending outside of a periphery of said multichip module packaging structure and having inner bond leads electrically bonded to ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit disposed about a periphery thereof; a multi-layer laminate board mechanically bonded over said second surface of said thin film multilayer interconnect circuit and over said inner bond leads of said lead frame, said multilayer laminate board having a first layer including conductive pads extending outward from about an inner periphery thereof, said multilayer laminate board further having a second layer including apertures formed therethrough, said apertures aligned with outwardly extending portions of said conductive pads and exposing an upper surface of said conductive pads.

Claim 31

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die disposed in said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having a first surface bonded to said first surface of said thin film multilayer interconnect circuit in a position such that said plurality of first bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of first I/O connection pads wire bonded to corresponding ones of said plurality of first bonding pads of said thin film multilayer interconnect circuit; at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; and a leadframe having outer leads extending outside of a periphery of said multichip module packaging structure and having inner bond leads electrically bonded to ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit disposed about a periphery thereof; a multi-layer laminate board mechanically bonded over said second surface of said thin film multilayer interconnect circuit and over said inner bond leads of said lead frame, said multilayer laminate board having a first layer including conductive pads extending outward from about an inner periphery thereof, said multilayer laminate board further having a second layer including apertures formed therethrough, said apertures aligned with outwardly extending portions of said conductive pads and exposing an upper surface of said conductive pads.

Claim 32

The multichip module packaging structure of claim 25 further including a layer of encapsulant disposed over said at least one first and second integrated circuit die.

Claim 33

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having first and second surfaces, wherein on said first surface thereof, a plurality of first I/O connection pads in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned for mating said plurality of first I/O connection pads with a plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; at least one second integrated circuit die disposed on said second surface of said at least one first integrated circuit die, said at least one second integrated circuit die having a first surface bonded to said second surface of said at least one first integrated circuit die in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die and said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; and at least one third integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that a plurality of third bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one third integrated circuit die, said at least one third integrated circuit die including a plurality of third I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of third I/O connection pads wire bonded to corresponding ones of said plurality of third bonding pads of said thin film multilayer interconnect circuit.

Claim 34

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having first and second surfaces, wherein on said first surface thereof, a plurality of first I/O connection pads in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned for mating said plurality of first I/O connection pads with a plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; at least one second integrated circuit die disposed on said second surface of said at least one first integrated circuit die, said at least one second integrated circuit die having a first surface bonded to said second surface of said at least one first integrated circuit die in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die and said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; and at least one third integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that a plurality of third bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one third integrated circuit die, said at least one third integrated circuit die including a plurality of third I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of third I/O connection pads wire bonded to corresponding ones of said plurality of third bonding pads of said thin film multilayer interconnect circuit.

Claim 35

The multichip module packaging structure of claim 26 wherein said first I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

Claim 36

The multichip module packaging structure of claim 26 wherein said first I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

Claim 37

The multichip module packaging structure of claim 26 wherein said first I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

Claim 38

The multichip module packaging structure of claim 26 further including a layer of encapsulant disposed over said plurality of integrated circuit dice.

Claim 39

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die disposed within said at least one chip mounting cavity and on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having first and second surfaces, wherein a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned for mating said plurality of first I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; at least one second integrated circuit die disposed within said at least one chip mounting cavity, said at least one second integrated circuit die having a first surface bonded to said second surface of said at least one first integrated circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die and of said at least one second integrated circuit, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; at least one third integrated circuit die disposed on said first surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die having first and second surfaces, wherein a plurality of third I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die aligned for mating said plurality of third I/O connection pads with said plurality of first bonding pads, said third I/O connection pads electrically connected to said first bonding pads; and at least one fourth integrated circuit die having a first surface bonded to said second surface of said at least one third integrated circuit die in a position such that said plurality of fourth bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one third integrated circuit die and said at least one fourth integrated circuit die, wherein said at least one fourth integrated circuit die having a plurality of fourth I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of fourth I/O connection pads wire bonded to corresponding ones of said plurality of fourth bonding pads of said thin film multilayer interconnect circuit.

Claim 40

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one first integrated circuit die disposed within said at least one chip mounting cavity and on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having first and second surfaces, wherein a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned for mating said plurality of first I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; at least one second integrated circuit die disposed within said at least one chip mounting cavity, said at least one second integrated circuit die having a first surface bonded to said second surface of said at least one first integrated circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die and of said at least one second integrated circuit, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; at least one third integrated circuit die disposed on said first surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die having first and second surfaces, wherein a plurality of third I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die aligned for mating said plurality of third I/O connection pads with said plurality of first bonding pads, said third I/O connection pads electrically connected to said first bonding pads; and at least one fourth integrated circuit die having a first surface bonded to said second surface of said at least one third integrated circuit die in a position such that said plurality of fourth bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one third integrated circuit die and said at least one fourth integrated circuit die, wherein said at least one fourth integrated circuit die having a plurality of fourth I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of fourth I/O connection pads wire bonded to corresponding ones of said plurality of fourth bonding pads of said thin film multilayer interconnect circuit.

Claim 41

The multichip module packaging structure of claim 31 wherein said first I/O connection pads and said first bonding pads, and said third I/O connection pads and said third bonding pads are electrically connected by solder ball reflow.

Claim 42

The multichip module packaging structure of claim 31 wherein said first I/O connection pads are electrically bonded to said first bonding pads, and said third I/O connection pads are electrically bonded to said third bonding pads by gold to gold with adhesive attach.

Claim 43

The multichip module packaging structure of claim 31 wherein said first I/O connection pads are electrically bonded to said first bonding pads, and said third I/O connection pads are electrically bonded to said third bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

Claim 44

The multichip module packaging structure of claim 31 further including a layer of encapsulant disposed over said plurality of integrated circuit dice.