US5608261A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High performance and high capacitance package with improved thermal dissipation
Assignee: Intel Corp
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Filing: 1994-12-28
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Granted: 1997-03-04
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Expires: 2014-12-28
Abstract
Abstract A thermally dissipative IC package which can accommodate large discrete capacitors. The package substrate incorporates a recessed region on one of its surfaces which is separate from the region in which the IC device is placed. Inside this recessed region is placed a discrete capacitor such that the entire capacitor resides below the surface of the substrate within the recessed region. Finally, a metal plate is attached to the surface of the substrate, unencumbered by the discrete capacitor.
Inventors
- 👤 Bidyut K. Bhattacharyya
- 👤 Shigeo Tanahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:39
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W40/00; H10W40/20; H10W40/22; H10W44/00; H10W44/601; H10W70/682; H10W70/685; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W90/00; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
94 words
A package configured to house an integrated circuit comprising: a substrate having a surface; at least one recessed region within said surface of said substrate; at least one discrete capacitor disposed below said surface of said substrate within said recessed region; at least one through hole within said substrate, said through hole provided to house said integrated circuit; and at least one metal plate attached to said surface of said substrate, said metal plate configured to hermetically seal said capacitor within said recessed region and to hermetically seal one side of said through hole.
Claim 2
Dependent Claim
94 words
A package configured to house an integrated circuit comprising: a substrate having a surface; at least one recessed region within said surface of said substrate; at least one discrete capacitor disposed below said surface of said substrate within said recessed region; at least one through hole within said substrate, said through hole provided to house said integrated circuit; and at least one metal plate attached to said surface of said substrate, said metal plate configured to hermetically seal said capacitor within said recessed region and to hermetically seal one side of said through hole.
Claim 3
Dependent Claim
46 words
The package of claim 1 further comprising a ground plane of said package electrically coupled to both a first terminal end of said capacitor and to said metal plate, and a power plane of said package electrically coupled to a second terminal end of said capacitor.
Claim 4
Dependent Claim
11 words
The package of claim 1 wherein said metal plate comprises copper.
Claim 5
Dependent Claim
16 words
The package of claim 3 wherein said integrated circuit is thermally coupled to said metal plate.
Claim 6
Dependent Claim
14 words
The package of claim 1 wherein said package is a pin grid array package.
Claim 7
Dependent Claim
14 words
The package of claim 1 wherein said package is a ball grid array package.
Claim 8
Dependent Claim
107 words
A ceramic package configured to house an integrated circuit, said ceramic package further comprising: a ground plane electrically coupled to a ground line; a power plane electrically coupled to a power line; at least one recessed region within a surface of said package; at least one discrete capacitor disposed below said surface of said package within said recessed region and having a first terminal end electrically coupled to said ground plane and a second terminal end electrically coupled to the power plane; and at least one metal plate attached to said surface of said package, said plate configured to hermetically seal the capacitor within said recessed region.
Claim 9
Dependent Claim
107 words
A ceramic package configured to house an integrated circuit, said ceramic package further comprising: a ground plane electrically coupled to a ground line; a power plane electrically coupled to a power line; at least one recessed region within a surface of said package; at least one discrete capacitor disposed below said surface of said package within said recessed region and having a first terminal end electrically coupled to said ground plane and a second terminal end electrically coupled to the power plane; and at least one metal plate attached to said surface of said package, said plate configured to hermetically seal the capacitor within said recessed region.
Claim 10
Dependent Claim
39 words
The package of claim 7 further comprising an integrated circuit (IC) attached to said plate such that said plate hermetically seals said IC within said package and said plate conducts heat generated by said IC away from said IC.
Claim 11
Dependent Claim
26 words
The package of claim 7 wherein a plurality of capacitors are disposed within a plurality of recessed regions in a substantially similar manner as said capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |