Patent US5794070A successfully refreshed from Google Patents.
US5794070A
Expired / Lapsed
US
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Method and apparatus for fast DMA transfer on an industry standard architecture (ISA) bus
Assignee: Intel Corp
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Filing: 1996-10-16
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Granted: 1998-08-11
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Expires: 2016-10-16
Abstract
Abstract A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.
Inventors
- 👤 Jeffrey L. Rabe
- 👤 Dave Smyth
- 👤 David D. Lent
- 👤 Sathyamurthi Sadhasivan
- 👤 Dahmane Dahmani
- 👤 Stephen T. Rowland
- 👤 James S. Coke
- 👤 Mitchell W. Dale
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
150 words
A method for a direct memory access (DMA) transfer on an industry standard architecture (ISA) compatible bus comprising at least one DMA device, said method comprising the steps of: generating a bus clock for providing timing for said DMA transfer; setting-up said DMA transfer on said ISA compatible bus including selecting a DMA device for said DMA transfer and specifying a transfer mode for said DMA transfer during a first clock period; generating an address during a second clock period specifying a location in memory for a DMA transfer cycle; asserting a command signal, said command signal comprising an IOW# for an ISA-compatible input/output (I/O) write operation and an IOR# for an ISA-compatible I/O read operation, on said ISA compatible bus during a third clock period for said DMA transfer cycle; and providing data on said ISA compatible bus for said DMA transfer cycle during assertion of said command signal.
Claim 2
Independent Claim
150 words
A method for a direct memory access (DMA) transfer on an industry standard architecture (ISA) compatible bus comprising at least one DMA device, said method comprising the steps of: generating a bus clock for providing timing for said DMA transfer; setting-up said DMA transfer on said ISA compatible bus including selecting a DMA device for said DMA transfer and specifying a transfer mode for said DMA transfer during a first clock period; generating an address during a second clock period specifying a location in memory for a DMA transfer cycle; asserting a command signal, said command signal comprising an IOW# for an ISA-compatible input/output (I/O) write operation and an IOR# for an ISA-compatible I/O read operation, on said ISA compatible bus during a third clock period for said DMA transfer cycle; and providing data on said ISA compatible bus for said DMA transfer cycle during assertion of said command signal.
Claim 3
Dependent Claim
94 words
The method for a direct memory access (DMA) transfer as claimed in claim 1 wherein the step of setting-up said DMA transfer further comprises the steps of: asserting a DREQ signal to request said DMA transfer on said bus by said DMA device; generating a transfer request for use of said bus for said DMA transfer; granting use of said bus for said DMA transfer; and issuing a DACK# signal to said DMA device during said first clock period, said DACK# signal signifying to said DMA device completion of setting-up of said DMA transfer.
Claim 4
Dependent Claim
94 words
The method for a direct memory access (DMA) transfer as claimed in claim 1 further including additional DMA transfer cycles, each of said additional DMA transfer cycles being two clock periods in duration, comprising the steps of: de-asserting said command signal during a fourth clock period; generating an address specifying a location in memory for an additional DMA transfer cycle during said fourth clock period; asserting said command signal on said bus during a fifth clock period; providing data on said bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 5
Dependent Claim
103 words
The method for a direct memory access (DMA) transfer as claimed in claim 1 further including additional DMA transfer cycles, each of said DMA transfer cycles being three clock periods in duration, comprising the steps of: de-asserting said command signal during a fourth clock period; de-asserting said command signal during a fifth clock period; generating an address specifying a location in memory for an additional DMA transfer cycle during said fifth clock period; asserting said command signal on said bus during a sixth clock period; and providing data on said bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 6
Dependent Claim
23 words
The method for a direct memory access (DMA) transfer as claimed in claim 1 wherein said DMA device comprises an IDE standard controller.
Claim 7
Independent Claim
204 words
An apparatus for generating a direct memory access (DMA) transfer on an industry standard architecture (ISA) compatible bus comprising: at least one DMA device coupled to said ISA compatible bus; bus controller means coupled to said ISA compatible bus for controlling operation of said ISA compatible bus, said bus controller means including a bus clock means for generating a bus clock to provide timing for said DMA transfer, said bus controller means asserting a command signal on said ISA compatible bus during a third clock period for a DMA transfer cycle, said command signal comprising an IOW# for an ISA-compatible I/O write operation and an IOR# for an ISA-compatible I/O read operation; and DMA controller means coupled to said bus controller means and said ISA compatible bus for effectuating a DMA transfer, said DMA controller means comprising a set-up means for selecting a DMA device for said DMA transfer and initializing said DMA device by specifying a transfer mode for said DMA transfer, said DMA controller means generating an address specifying a location in memory for said DMA transfer cycle during a second clock period, and providing data on said ISA compatible bus for said DMA transfer cycle during assertion of said command signal.
Claim 8
Independent Claim
204 words
An apparatus for generating a direct memory access (DMA) transfer on an industry standard architecture (ISA) compatible bus comprising: at least one DMA device coupled to said ISA compatible bus; bus controller means coupled to said ISA compatible bus for controlling operation of said ISA compatible bus, said bus controller means including a bus clock means for generating a bus clock to provide timing for said DMA transfer, said bus controller means asserting a command signal on said ISA compatible bus during a third clock period for a DMA transfer cycle, said command signal comprising an IOW# for an ISA-compatible I/O write operation and an IOR# for an ISA-compatible I/O read operation; and DMA controller means coupled to said bus controller means and said ISA compatible bus for effectuating a DMA transfer, said DMA controller means comprising a set-up means for selecting a DMA device for said DMA transfer and initializing said DMA device by specifying a transfer mode for said DMA transfer, said DMA controller means generating an address specifying a location in memory for said DMA transfer cycle during a second clock period, and providing data on said ISA compatible bus for said DMA transfer cycle during assertion of said command signal.
Claim 9
Dependent Claim
116 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 6 wherein said set-up means in said DMA controller means further comprises: bus arbitration means coupled to said bus controller means and also coupled to said DMA controller means for granting control of said bus; said DMA device asserting a DREQ signal to request a DMA transfer on said bus; and said DMA controller means generating a transfer request for use of said bus for said DMA transfer to said bus arbitration means, and issuing a DACK# signal to said DMA device when granted use of said bus, said DACK# signal signifying to said DMA device completion of setting-up of said DMA transfer.
Claim 10
Dependent Claim
107 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 6 further including additional DMA transfer cycles, each of said additional transfer cycles being two clock periods in duration, comprising: said bus controller means de-asserting said command signal during a fourth clock period and asserting said command signal on said bus during a fifth clock period for an additional DMA transfer cycle; and said DMA controller means generating an address specifying a location in memory for said additional DMA transfer cycle during said fourth clock period and providing data on said bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 11
Dependent Claim
111 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 6 further including additional DMA transfer cycles, each of said additional transfer cycles being three clock periods in duration, comprising: said bus controller means de-asserting said command signal during a fourth clock period, said command signal remaining de-asserted during a fifth clock period, and asserting said command signal on said bus during a sixth clock period; and said DMA controller means generating an address specifying a location in memory for an additional DMA transfer cycle during said fifth clock period and providing data on said bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 12
Dependent Claim
23 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 6 wherein said DMA device comprises an IDE-compatible hard drive.
Claim 13
Independent Claim
168 words
An apparatus for generating a direct memory access (DMA) transfer on an industry standard architecture (ISA) bus comprising: at least one I/O device coupled to said ISA bus; an ISA bus controller coupled to said ISA bus for controlling operation of said ISA bus, said ISA bus controller receiving a bus clock to provide timing for said DMA transfer, said ISA bus controller asserting a command signal on said ISA bus during a third clock period for a DMA transfer cycle; and a DMA controller coupled to said ISA bus controller and said ISA bus for effectuating a DMA transfer, said DMA controller setting-up a DMA transfer on said ISA bus with an I/O device and specifying a transfer mode for said DMA transfer during a first clock period, said DMA controller generating an address specifying a location in memory for said DMA transfer cycle during a second clock period, and providing data on said ISA bus for said DMA transfer cycle during assertion of said command signal.
Claim 14
Independent Claim
168 words
An apparatus for generating a direct memory access (DMA) transfer on an industry standard architecture (ISA) bus comprising: at least one I/O device coupled to said ISA bus; an ISA bus controller coupled to said ISA bus for controlling operation of said ISA bus, said ISA bus controller receiving a bus clock to provide timing for said DMA transfer, said ISA bus controller asserting a command signal on said ISA bus during a third clock period for a DMA transfer cycle; and a DMA controller coupled to said ISA bus controller and said ISA bus for effectuating a DMA transfer, said DMA controller setting-up a DMA transfer on said ISA bus with an I/O device and specifying a transfer mode for said DMA transfer during a first clock period, said DMA controller generating an address specifying a location in memory for said DMA transfer cycle during a second clock period, and providing data on said ISA bus for said DMA transfer cycle during assertion of said command signal.
Claim 15
Dependent Claim
129 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 11 further comprising: a bus arbiter coupled to said ISA bus controller and said DMA controller for granting control of said ISA bus; mode registers within said DMA controller for specifying a transfer mode for said DMA transfer; DREQ means within said I/O device for asserting a DREQ signal to request a DMA transfer on said ISA bus; and transfer request means within said DMA controller for making a transfer request to said bus arbiter for use of said ISA bus for said DMA transfer, and issuing a DACK# signal to said I/O device when granted use of said ISA bus, said DACK# signal signifying to said I/O device completion of setting-up of said DMA transfer.
Claim 16
Dependent Claim
101 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 11 further including additional DMA transfer cycles, each of said additional transfer cycles being two clock periods in duration, comprising: said ISA bus controller de-asserting said command signal during a fourth clock period, and asserting said command signal on said bus during a fifth clock period; and said DMA controller generating an address specifying a location in memory during said fourth clock period for an additional DMA transfer cycle and providing data on said ISA bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 17
Dependent Claim
113 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 11 further including additional DMA transfer cycles, each of said additional DMA transfer cycles being three clock periods in duration, comprising: said ISA bus controller de-asserting said command signal during a fourth clock period, said command signal remaining de-asserted during a fifth clock period, and asserting said command signal on said ISA bus during a sixth clock period; and said DMA controller generating an address specifying a location in memory during said fifth clock period for an additional DMA transfer cycle and providing data on said ISA bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 18
Dependent Claim
23 words
The apparatus for a direct memory access (DMA) transfer as claimed in claim 11 wherein said I/O device comprises an IDE-compatible hard drive.
Claim 19
Dependent Claim
283 words
A computer system comprising: processing means; storage means; first bus means, wherein said first bus means couples said processing means to said storage means; direct memory access (DMA) device means for providing functions to said computer system, said DMA device means being interfaced with said computer system via DMA transfers; second bus means, wherein said second bus means couples a plurality of I/O devices to said computer system; and system input/output (SIO) interface means coupled to said first bus means and said second bus means for interfacing said processing means and storage means to said plurality of I/O devices by generating DMA transfer cycles, said SIO interface means comprising bus controller means coupled to said second bus means for controlling operation of said second bus means, said bus controller means including bus clock means for generating a bus clock to provide timing for said DMA transfer cycles, said bus controller means asserting a command signal on said second bus means during a third clock period; DMA controller means coupled to said bus controller means and said second bus means for effectuating a DMA transfer, said DMA controller means comprising a set-up means for setting-up a DMA transfer on said second bus means with a DMA device and specifying a transfer mode for said DMA transfer during a first clock period, said DMA controller means generating an address specifying a location in memory for a DMA transfer cycle during a second clock period, and providing data on said second bus means for said DMA transfer cycle during assertion of said command signal; and DMA transfer means for providing additional DMA transfer cycles, each of said DMA transfer cycles being two clock periods in duration.
Claim 20
Dependent Claim
283 words
A computer system comprising: processing means; storage means; first bus means, wherein said first bus means couples said processing means to said storage means; direct memory access (DMA) device means for providing functions to said computer system, said DMA device means being interfaced with said computer system via DMA transfers; second bus means, wherein said second bus means couples a plurality of I/O devices to said computer system; and system input/output (SIO) interface means coupled to said first bus means and said second bus means for interfacing said processing means and storage means to said plurality of I/O devices by generating DMA transfer cycles, said SIO interface means comprising bus controller means coupled to said second bus means for controlling operation of said second bus means, said bus controller means including bus clock means for generating a bus clock to provide timing for said DMA transfer cycles, said bus controller means asserting a command signal on said second bus means during a third clock period; DMA controller means coupled to said bus controller means and said second bus means for effectuating a DMA transfer, said DMA controller means comprising a set-up means for setting-up a DMA transfer on said second bus means with a DMA device and specifying a transfer mode for said DMA transfer during a first clock period, said DMA controller means generating an address specifying a location in memory for a DMA transfer cycle during a second clock period, and providing data on said second bus means for said DMA transfer cycle during assertion of said command signal; and DMA transfer means for providing additional DMA transfer cycles, each of said DMA transfer cycles being two clock periods in duration.
Claim 21
Dependent Claim
131 words
The computer system as claimed in claim 16 wherein said SIO interface means further comprises DMA transfer means for providing additional DMA transfer cycles, each of said DMA transfer cycles, each of said DMA transfer cycles being two clock periods in duration, wherein said bus controller means de-asserts said command signal during a fourth clock period, and asserts said command signal on said second bus means during a fifth clock period, and said DMA controller means generating an address specifying a location in memory for an additional DMA transfer cycle during said fourth clock period for an additional DMA transfer when said DMA transfer is initialized for block or demand mode, and providing data on said second bus means for said additional DMA transfer cycle during assertion of said command signal.
Claim 22
Dependent Claim
130 words
The computer system as claimed in claim 16 wherein said SIO interface means further comprises: mode select means for specifying a transfer mode for DMA transfer; and DMA transfer means for providing additional DMA transfer cycles, each of said DMA transfer cycles being three clock periods in duration, wherein said bus controller means de-asserts said command signal during a fourth clock period, said command signal remaining de-asserted during a fifth clock period, and asserts said command signal on said second bus means during a sixth clock period, said DMA controller means generating an address specifying a location in memory for an additional DMA transfer cycle during said fifth clock period and providing data on said second bus means for said additional DMA transfer cycle during assertion of said command signal.
Claim 23
Dependent Claim
249 words
A computer system comprising: a central processing unit (CPU); main memory; an internal bus coupling said main memory to said CPU; a plurality of I/O devices for providing a plurality of functions to said computer system, said plurality of I/O devices being interfaced with said computer system via DMA transfers; an industry standard architecture (ISA) bus, wherein said ISA bus couples said plurality of I/O devices to said computer system; and a system input/output (SIO) interface coupled to said internal bus and said ISA bus for interfacing said main memory to said plurality of I/O devices by generating DMA transfer cycles, said SIO interface comprising; an ISA bus controller coupled to said ISA bus for controlling operation of said ISA bus, said ISA bus controller receiving a bus clock to provide timing for said DMA transfer cycles, said ISA bus controller asserting a command signal on said ISA bus during a third clock period for a DMA transfer cycle, a DMA controller coupled to said ISA bus controller and said ISA bus for effectuating a DMA transfer, said DMA controller setting-up a DMA transfer on said ISA bus with an I/O device during a first clock period, said DMA controller generating an address specifying a location in memory for said DMA transfer cycle during a second clock period, and providing data on said ISA bus for said DMA transfer cycle during assertion of said command signal; and mode select registers for specifying a transfer mode for DMA transfer cycle.
Claim 24
Dependent Claim
249 words
A computer system comprising: a central processing unit (CPU); main memory; an internal bus coupling said main memory to said CPU; a plurality of I/O devices for providing a plurality of functions to said computer system, said plurality of I/O devices being interfaced with said computer system via DMA transfers; an industry standard architecture (ISA) bus, wherein said ISA bus couples said plurality of I/O devices to said computer system; and a system input/output (SIO) interface coupled to said internal bus and said ISA bus for interfacing said main memory to said plurality of I/O devices by generating DMA transfer cycles, said SIO interface comprising; an ISA bus controller coupled to said ISA bus for controlling operation of said ISA bus, said ISA bus controller receiving a bus clock to provide timing for said DMA transfer cycles, said ISA bus controller asserting a command signal on said ISA bus during a third clock period for a DMA transfer cycle, a DMA controller coupled to said ISA bus controller and said ISA bus for effectuating a DMA transfer, said DMA controller setting-up a DMA transfer on said ISA bus with an I/O device during a first clock period, said DMA controller generating an address specifying a location in memory for said DMA transfer cycle during a second clock period, and providing data on said ISA bus for said DMA transfer cycle during assertion of said command signal; and mode select registers for specifying a transfer mode for DMA transfer cycle.
Claim 25
Dependent Claim
104 words
The computer system as claimed in claim 19 wherein said SIO interface further comprises: a DMA transfer cycle, said DMA transfer cycle being two clock periods in duration, for providing additional DMA transfer cycles, wherein said ISA bus controller de-asserts said command signal during a fourth clock period, and asserts said command signal on said ISA bus during a fifth clock period, and said DMA controller generating an address specifying a location in memory for an additional DMA transfer cycle during said fourth clock period and providing data on said ISA bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 26
Dependent Claim
127 words
The computer system as claimed in claim 19 wherein said SIO interface further comprises: mode select registers for specifying a transfer mode for a DMA transfer cycle; and a DMA transfer cycle, said DMA transfer cycle being three clock periods in duration, for providing additional DMA transfer cycles, wherein said ISA bus controller deasserts said command signal during a fourth clock period, said command signal remaining de-asserted during a fifth clock period, and asserts said command signal on said ISA bus during a sixth clock period, said DMA controller generating an address specifying a location in memory for an additional DMA transfer cycle during said fifth clock period and providing data on said ISA bus for said additional DMA transfer cycle during assertion of said command signal.
Claim 27
Independent Claim
206 words
A method for a direct memory access (DMA) transfer on a bus comprising at least one DMA device, said method comprising the steps of: generating a bus clock having clock cycles for providing timing for said DMA transfer; setting up a DMA transfer on said bus including selecting a DMA device for said DMA transfer and specifying a transfer mode for said DMA transfer during a first clock period; asserting an address on said bus during a first clock period, identifying said DMA device selected; asserting a command signal on said bus by transitioning said command signal from a first state to a second state during a second clock period for said DMA transfer; providing data on said bus for said DMA transfer during activation of said command signal; transitioning said command signal from said second state to said first state during a third clock period to signify termination of said DMA transfer; and deasserting said command signal by transitioning said command signal from said second state to said first state at a fourth clock period, said fourth clock period occurring at a number of clock cycles after the third clock period, the number of cycles after the third clock period depending on the DMA device.
Claim 28
Independent Claim
206 words
A method for a direct memory access (DMA) transfer on a bus comprising at least one DMA device, said method comprising the steps of: generating a bus clock having clock cycles for providing timing for said DMA transfer; setting up a DMA transfer on said bus including selecting a DMA device for said DMA transfer and specifying a transfer mode for said DMA transfer during a first clock period; asserting an address on said bus during a first clock period, identifying said DMA device selected; asserting a command signal on said bus by transitioning said command signal from a first state to a second state during a second clock period for said DMA transfer; providing data on said bus for said DMA transfer during activation of said command signal; transitioning said command signal from said second state to said first state during a third clock period to signify termination of said DMA transfer; and deasserting said command signal by transitioning said command signal from said second state to said first state at a fourth clock period, said fourth clock period occurring at a number of clock cycles after the third clock period, the number of cycles after the third clock period depending on the DMA device.
Claim 29
Dependent Claim
19 words
The method of claim 22, wherein the fourth clock period occurs two clock cycles after the third clock period.
Claim 30
Dependent Claim
19 words
The method of claim 22, wherein the fourth clock period occurs three clock cycles after the third clock period.
Claim 31
Dependent Claim
78 words
The method of claim 22, further comprising the steps of: grouping DMA devices that have been set up during the first clock period such that all DMA devices in a particular group have a common maximum supportable DMA transfer note, the DMA transfer rate being measured in clock cycles; and reasserting and subsequently deasserting the command signal once for each group, such that each group provides data on said bus during a corresponding assertion of said command signal.
Claim 32
Dependent Claim
37 words
The method of claim 25, wherein the step of reasserting and subsequently deasserting the command signal occupies a number of clock cycles such that at least one group transfers data during each assertion of said command signal.
References Cited (Backward Citations)
US5111425A
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |