Patent US5793993A successfully refreshed from Google Patents.
US5793993A
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Method for transmitting bus commands and data over two wires of a serial bus
Assignee: Intellectual Ventures I LLC
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Filing: 1995-08-18
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Granted: 1998-08-11
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Expires: 2015-08-18
Abstract
Abstract A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. All bus transactions over the bus occur under bus dispatch commands. If a peripheral device interrupts the bus dispatch, bus dispatch issues commands over the bus to determine which device caused the interrupt and what service is being requested by the device. The bus dispatch may then turn control of the data and clock lines over to the peripheral device for a limited amount of time depending on the service requested. New peripheral devices can be connected onto the bus and unused peripheral devices can be disconnected from the bus while the bus is operating without causing a bus failure. Similarly, bus dispatch may enter a low power sleep mode from which it may be awakened by a peripheral device. In some embodiments, additional lines such as battery charging lines and/or signal lines for other serial buses such as RS-232 and RS-422 are provided.
Inventors
- 👤 Walter F. Broedner
- 👤 Anthony M. Faddell
- 👤 Stephen G. Perlman
- 👤 John E. Watkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:48
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4282; G06F13/4291
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
101 words
A method for transmitting bus commands and data over two wires of a serial bus comprising: transmitting a bus command over said two wires by transmitting a command clock signal over a first wire of said two wires, and transmitting a bus command over a second wire of said two wires; and transmitting data over said two wires by transmitting data over said first wire of said two wires and transmitting a data clock signal over said second wire of said two wires wherein only one of said bus command and data is transmitted over said two wires at a time.
Claim 2
Independent Claim
101 words
A method for transmitting bus commands and data over two wires of a serial bus comprising: transmitting a bus command over said two wires by transmitting a command clock signal over a first wire of said two wires, and transmitting a bus command over a second wire of said two wires; and transmitting data over said two wires by transmitting data over said first wire of said two wires and transmitting a data clock signal over said second wire of said two wires wherein only one of said bus command and data is transmitted over said two wires at a time.
Claim 3
Dependent Claim
45 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 1 wherein transmitting said bus command over said second wire of said two wires further comprises: transmitting a plurality of bits of said bus command with a predetermined state.
Claim 4
Dependent Claim
46 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 2 wherein transmitting said plurality of bits of said bus command with a predetermined state further comprises: transmitting first and second bits of said bus command with a predetermined state.
Claim 5
Dependent Claim
32 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 3 wherein said predetermined state comprises said first and second bits having a logic one level.
Claim 6
Dependent Claim
37 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 1 wherein transmitting said bus command over said second wire of said two wires further comprises: transmitting a multi-byte bus command.
Claim 7
Dependent Claim
48 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 5 wherein transmitting said multi-byte bus command over said second wire of said two wires further comprises: transmitting first and second bits of a first bus command byte with a predetermined state.
Claim 8
Dependent Claim
54 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 5 wherein transmitting said multi-byte bus command over said second wire of said two wires further comprises: transmitting a plurality of address bits wherein said address bits identify a peripheral device that is to receive the bus command.
Claim 9
Dependent Claim
61 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 7 wherein transmitting said multi-byte bus command over said second wire of said two wires further comprises: transmitting a microcontroller bit wherein upon said microcontroller bit having a predetermined state, a portion of said bus command is passed to a microcontroller in said peripheral device.
Claim 10
Dependent Claim
53 words
A method for transmitting bus commands and data over a two-wire serial bus as in claim 1 wherein transmitting said bus command over said second wire of said two wires further comprises: transmitting a parity bit wherein said parity bit is set so that bits of the bus command have a predetermined parity.
Claim 11
Independent Claim
111 words
A method for transmitting bus commands and data over a serial bus comprising: transmitting bus commands and data over first and second wires of said serial bus wherein said transmitting bus commands and data further comprises: transmitting a bus command by transmitting a command clock signal over said first wire, and transmitting said bus command over said second wire; and transmitting data by transmitting data over said first wire, and transmitting a data clock signal over said second wire wherein only one of said bus command and data is transmitted over said first and second wires at a time; and transmitting interrupt signals over a third wire of said serial bus.
Claim 12
Independent Claim
111 words
A method for transmitting bus commands and data over a serial bus comprising: transmitting bus commands and data over first and second wires of said serial bus wherein said transmitting bus commands and data further comprises: transmitting a bus command by transmitting a command clock signal over said first wire, and transmitting said bus command over said second wire; and transmitting data by transmitting data over said first wire, and transmitting a data clock signal over said second wire wherein only one of said bus command and data is transmitted over said first and second wires at a time; and transmitting interrupt signals over a third wire of said serial bus.
Claim 13
Dependent Claim
32 words
A method for transmitting bus commands and data over a serial bus as in claim 10 further comprising: supplying a bus power supply voltage over a fourth wire of said serial bus.
Claim 14
Dependent Claim
30 words
A method for transmitting bus commands and data over a serial bus as in claim 11 further comprising: supplying a bus ground via a fifth wire of said serial bus.
Claim 15
Dependent Claim
42 words
A method for transmitting bus commands and data over a serial bus as in claim 11 further comprising: buffering said bus commands, data and interrupt signals on said first, second, and third lines respectively in each peripheral device on said serial bus.
Claim 16
Dependent Claim
35 words
A method for transmitting bus commands and data over a serial bus as in claim 13 further comprising: powering buffers used in said buffering step with said bus power supply voltage on said fourth wire.
Claim 17
Dependent Claim
40 words
A method for transmitting bus commands and data over a serial bus as in claim 10 wherein transmitting said bus command over said second wire further comprises: transmitting a plurality of bits of said bus command with a predetermined state.
Claim 18
Dependent Claim
45 words
A method for transmitting bus commands and data over a serial bus as in claim 15 wherein transmitting said plurality of bits of said bus command with a predetermined state further comprises: transmitting first and second bits of said bus command with said predetermined state.
Claim 19
Dependent Claim
31 words
A method for transmitting bus commands and data over a serial bus as in claim 16 wherein said predetermined state comprises said first and second bits having a logic one level.
Claim 20
Dependent Claim
32 words
A method for transmitting bus commands and data over a serial bus as in claim 10 wherein transmitting said bus command over said second wire further comprises: transmitting a multi-byte bus command.
Claim 21
Dependent Claim
42 words
A method for transmitting bus commands and data over a serial bus as in claim 18 wherein transmitting said multi-byte bus command over said second wire further comprises: transmitting first and second bits of a first command byte with a predetermined state.
Claim 22
Dependent Claim
49 words
A method for transmitting bus commands and data over a serial bus as in claim 18 wherein transmitting said multi-byte bus command over said second wire further comprises: transmitting a plurality of address bits wherein said address bits identify a peripheral device that is to receive the bus command.
Claim 23
Dependent Claim
56 words
A method for transmitting bus commands and data over a serial bus as in claim 18 wherein transmitting said multi-byte bus command over said second wire further comprises: transmitting a microcontroller bit wherein upon said microcontroller bit having a predetermined state, a portion of said bus command is passed to a microcontroller in a peripheral device.
Claim 24
Dependent Claim
48 words
A method for transmitting bus commands and data over a serial bus as in claim 10 wherein transmitting said bus command over said second wire further comprises: transmitting a parity bit wherein said parity bit is set so that bits of the bus command have a predetermined parity.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |