US4675864A
Expired / Lapsed
US
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Serial bus system
Assignee: HP Inc
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Filing: 1985-06-04
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Granted: 1987-06-23
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Expires: 2005-06-04
Abstract
Abstract A serial bus system in which frames are sent from a central station to a plurality of substations over a first conductor and information is sent from the substation to the central station over a second conductor. Each transmitted frame contains bits identifying whether it is for address, data or a command. An addressed substation sends a handshake back to the central station by changing the logic level of the second conductor. An address frame contains a bit indicating whether a message is to be written into a register of a substation or read from a register therein. Any substation can interrupt to request service from the central station by changing the logic level of the second conductor if the last command on the first conductor is an unaddress command indicating the end of a message.
Inventors
- 👤 Genevieve M. Bliek
- 👤 Kent W. Luehman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:08
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
204 words
A serial bus system comprising a central station and a plurality of subsidiary stations, each of said stations having its own processor, each of said processors having an input and an output, a first conductor forming a single path between the output of the processor for said central station and the inputs of the processors for said subsidiary station, a second conductor forming a single path between the outputs of the processors for said substations and the input of the processor for said central station, the processor for said central station being programmed to place the bits of a frame onto said first conductor in series, each of said processors for said subsidiary stations being programmed to respond to a frame on said first conductor that represents its address by changing the state of said second conductor for a first interval after the receipt of each frame if the frame does not have proper form or the microprocessor for the addressed station cannot process the frame or by changing the state of said second conductor for a second interval that is longer than said first interval if the frame has the proper form and the microprocessor for the addressed station can process the frame.
Claim 2
Dependent Claim
204 words
A serial bus system comprising a central station and a plurality of subsidiary stations, each of said stations having its own processor, each of said processors having an input and an output, a first conductor forming a single path between the output of the processor for said central station and the inputs of the processors for said subsidiary station, a second conductor forming a single path between the outputs of the processors for said substations and the input of the processor for said central station, the processor for said central station being programmed to place the bits of a frame onto said first conductor in series, each of said processors for said subsidiary stations being programmed to respond to a frame on said first conductor that represents its address by changing the state of said second conductor for a first interval after the receipt of each frame if the frame does not have proper form or the microprocessor for the addressed station cannot process the frame or by changing the state of said second conductor for a second interval that is longer than said first interval if the frame has the proper form and the microprocessor for the addressed station can process the frame.
Claim 3
Dependent Claim
104 words
A serial bus system as set forth in claim 1 wherein the processor for said central station inserts a parity bit into a frame and wherein the processors for the substations are programmed to check the parity of a frame on the first conductor if that station is addressed and to change the state of said second conductor for said first interval if the parity of a frame does not agree with the parity bit inserted by the central station or to change the state of said second conductor for said second interval if the parity of the frame agrees with the parity bit.
Claim 4
Dependent Claim
40 words
A serial bus system as set forth in claim 2 wherein the processor for the central station is programmed to retransmit a frame on said first conductor if the state of said second conductor is changed for said first interval.
Claim 5
Dependent Claim
75 words
A serial bus system as set forth in claim 1 wherein the processor for said central station transmits a particular frame on said first conductor at the end of each message and wherein the processors for said substations are programmed to determine whether their subsidiary stations are requesting service from the central station and for changing the logic level of said second conductor after the receipt of said particular frame if such request is present.
Claim 6
Dependent Claim
49 words
A serial bus system as set forth in claim 4 wherein the processor for said central station is programmed to poll said subsidiary stations to see which is requesting service from the central station when said second conductor changes state after the central station has transmitted said particular frame.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-22 | 1990-12-22 | 1991-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-22 | 1994-12-22 | 1995-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-22 | 1998-12-22 | 1999-06-23 | $7700.00 | Window Closed / Lapsed |