Input circuit

Claim 2

An input circuit in which potentials present within first and second ranges correspond to first and second binary logics, respectively, comprising; (a) an input line on which an input potential is transmitted, (b) first driving means for forcibly putting said input potential in said second range when a first driving control signal is activated, and (c) first driving control means for activating said first driving control signal for a constant period after a first transition in which said input potential is transferred from said first range to said second range.

Claim 3

The input circuit according to claim 1, wherein said input potential also performs a second transition from said second range to said first range, said first driving control means comprising; (c-1) a delay element including an input end connected to said input line, and an output end for outputting a delay input signal, said delay input signal performing third and fourth transitions delayed for said constant period after first and second transitions respectively, (c-2) a first switch including a first end connected to said input line and a second end for outputting a first control signal, said first switch being non-conductive corresponding to the value of said delay input signal obtained by said third transition, and being conductive corresponding to the value of said delay input signal obtained by said fourth transition, and (c-3) a second switch including a first end to which a potential equivalent to said first driving control signal that is activated is given, and a second end for outputting said first driving control signal, said second switch being non-conductive if said first control signal is present within said first range, and being conductive if said first control signal is present within said second range.

Claim 4

The input circuit according to claim 2, wherein said delay element includes a series connection of plural inverters.

Claim 5

The input circuit according to claim 2, wherein said first switch is a transmission gate.

Claim 6

The input circuit according to claim 2, wherein said first driving control means further comprises; (c-4) a third switch including a first end to which a potential present within said first range is given, and a second end connected to said second end of said first switch for outputting said first control signal, said third switch being conductive/non-conductive complementarily to said first switch.

Claim 7

The input circuit according to claim 5, wherein said first driving control means further comprises; (c-5) a first potential specifying means including a first end to which a potential equivalent to said driving control signal which is deactivated is given, and a second end connected to said second end of said second switch.

Claim 8

The input circuit according to claim 6, wherein said first potential specifying means comprises; (c-5-1) a fourth switch including first and second ends connected to said first and second ends of said first potential specifying means respectively, said fourth switch being conductive if said delay input signal is present within said second range, and (c-5-2) a potential specified resistor connected to said fourth switch in parallel.

Claim 9

The input circuit according to claim 7, wherein said potential specified resistor is formed by a MOS transistor which includes first and second ends connected to said first and second ends of said first potential specifying means respectively, said MOS transistor being conductive/non-conductive respectively if said input potential is present within said first and second ranges.

Claim 10

The input circuit according to claim 6, wherein said first driving means comprises; (b-1) a driving MOS transistor including a source to which a first potential present at the farthest limit from said first range within said second range is given, a drain connected to said input line, and a gate electrode, said gate electrode of said driving MOS transistor being connected to said second end of said first potential specifying means, said first driving control signal being activated and deactivated within said first and second ranges respectively, and said first driving control means further comprises; (c-6) a voltage supporting element including a first end to which said first potential is given, and a second end connected to said first end of said first potential specifying means, said voltage supporting element supporting a voltage equal to a threshold voltage of said driving MOS transistor between said first and second ends.

Claim 11

The input circuit according to claim 2, wherein said first driving control means further comprises; (c-4) a differential input amplifier inserted between said input line and said input end of said delay element, the first input end, the second input end and the output end of said differential input amplifier being connected to said input line, a reference potential point, and said input end of said delay element respectively.

Claim 12

The input circuit according to claim 10, wherein said second input end of said differential input amplifier is connected to a reference potential point through a potential suppress resistor, and wherein the transition of a signal output from said output end of said differential input amplifier is delayed and transmitted to said second input end of said differential input amplifier.

Claim 13

The input circuit according to claim 11, wherein said first and second input ends of said differential input amplifier are inverted and non-inverted input ends respectively, said first driving control means further comprising; (c-5) an inverter including an input end connected to said output end of said differential input amplifier, and an output end connected to said second input end of said differential input amplifier.

Claim 14

The input circuit according to claim 1, further comprising; (d) a driving suppress resistor inserted between said input line and said first driving means.

Claim 15

The input circuit according to claim 2, further comprising; (d) second driving means for forcibly putting said input potential in said first range if a second driving control signal is activated, and (e) second driving control means for activating said second driving control signal for a constant period after a second transition in which said input potential is transferred from said second range to said first range.

Claim 16

The input circuit according to claim 14, wherein said second driving control means comprises; (e-1) a first switch including a first end connected to said input line and a second end for outputting a second control signal, said first switch being non-conductive corresponding to the value of said delay input signal obtained by said fourth transition, and being conductive corresponding to the value of said delay input signal obtained by said third transition, and (e-2) a second switch including a first end to which a potential equivalent to said driving control signal that is activated is given, and a second end for outputting said second driving control signal said second switch being conductive if said second control signal is present within said first range, and being non-conductive if said second control signal is present within said second range.

Claim 17

The input circuit according to claim 15, wherein said second driving control means further comprises; (e-3) a third switch including a first end to which a potential present within said second range is given, and a second end connected to said second end of said first switch of said second driving means for outputting said second control signal, said third switch being conductive/non-conductive complementarily to said first switch of said second driving means.

Claim 18

The input circuit according to claim 14, further comprising; (f) a first logic circuit that includes a first input end to which one of a pair of complementary output signals is input and a second input end to which said first driving control signal is sent, and outputs an OR function of data given to said first and second input ends to said first driving means, and (g) a second logic circuit that includes a first input end to which the other of said pair of complementary output signal is input and a second input end to which said second driving control signal is sent, and outputs an OR function of data given to said first and second input ends to said second driving means.

Claim 19

The input circuit according to claim 2, wherein said first driving control means further comprises; (c-4) a logic circuit gating an input signal for said delay element according to a switching signal, said logic circuit causing said first switch to be non-conductive and fixing said first control signal to a predetermined logic level in response to said switching signal.

Claim 20

The input circuit according to claim 14, further comprising: a delay element including first series connection of gates for said first driving control means and second series connection of gates for said second driving control means, said second driving control means further comprising; (c-4) logic gates inserted in said first and second series connection of gates in series for receiving a switching signal, said logic gates causing said first switch to be non-conductive and fixing said second control signal to a predetermined logic level in response to said switching signal.