Voltage multiplier with adjustable output level

Claim 2

A voltage multiplying circuit comprising: first and second switch transistors serially coupled between first and second reference voltages; third and fourth switch transistors serially coupled between said second reference voltage and an output terminal; a first capacitor having first terminal coupled to a common node between said first and second switch transistors, and a second terminal coupled to a common node between said third and fourth switch transistors; a second capacitor having a first terminal coupled to said output terminal, and a second terminal coupled to said first reference voltage; and a third capacitor having a first terminal coupled to said common node between said third and fourth switch transistors, and a second terminal coupled to said second reference voltage, wherein, by controlling an on/off timing of said switch transistors, and adjusting a size ratio of said third capacitor to said first capacitor, an output voltage level greater than a level of said second reference voltage and less than twice said level of said reference voltage can be generated at said output terminal.

Claim 3

The voltage multiplying circuit of claim 1 wherein the control signals to the first, second, third, and fourth switch transistors are driven by one of a first or second clock signal, wherein further the first clock signal has an opposite polarity to the second clock signal.

Claim 4

The voltage multiplying circuit of claim 2 wherein said first switch transistor is an N-channel MOS transistor, and each of said second, third, and fourth transistors is a P-channel MOS transistor.

Claim 5

The voltage multiplying circuit of claim 3 wherein said opposite polarity clock signals comprise non-overlapping clock signals of CLK1 and CLK2 having opposite polarity.

Claim 6

The voltage multiplying circuit of claim 4 wherein said first, second and fourth switch transistors each receive CLK1 at a respective gate terminal, and said second switch transistor receives CLK2 at a gate terminal.

Claim 7

The voltage multiplying circuit of claim 5 wherein said first reference voltage is ground and said second reference voltage is a primary power supply for the circuit.

Claim 8

A voltage multiplying circuit coupled between a power supply voltage and ground and having an output terminal comprising: a first MOS transistor having a first source/drain terminal coupled to the output terminal, a second source/drain terminal coupled to a first node N1, and a gate terminal coupled to a first clock signal; a second MOS transistor having a first source/drain terminal coupled to said first node N1, a second source/drain terminal coupled to the power supply voltage, and a gate terminal coupled to a second clock signal; a third MOS transistor having a first source/drain terminal coupled to the power supply voltage, a second source/drain terminal coupled to a second node N2, and a gate terminal coupled to said first clock signal; a fourth MOS transistor having a first source/drain terminal coupled to the second node N2, a second source/drain terminal coupled to ground and a gate terminal coupled to said first clock signal; a first capacitor having a first terminal coupled to said node N1 and a second terminal coupled to said node N2; a second capacitor having a first terminal coupled to the output terminal and a second terminal coupled to ground; and a third capacitor having a first terminal coupled to said first node N1, and a second terminal coupled to the power supply voltage.

Claim 9

A voltage multiplying circuit coupled between a power supply voltage and ground and having an output terminal comprising: a first MOS transistor having a first source/drain terminal coupled to the output terminal, a second source/drain terminal coupled to a first node N1, and a gate terminal coupled to a first clock signal; a second MOS transistor having a first source/drain terminal coupled to said first node N1, a second source/drain terminal coupled to the power supply voltage, and a gate terminal coupled to a second clock signal; a third MOS transistor having a first source/drain terminal coupled to the power supply voltage, a second source/drain terminal coupled to a second node N2, and a gate terminal coupled to said first clock signal; a fourth MOS transistor having a first source/drain terminal coupled to the second node N2, a second source/drain terminal coupled to ground and a gate terminal coupled to said first clock signal; a first capacitor having a first terminal coupled to said node N1 and a second terminal coupled to said node N2; a second capacitor having a first terminal coupled to the output terminal and a second terminal coupled to ground; and a third capacitor having a first terminal coupled to said first node N1, and a second terminal coupled to the power supply voltage.

Claim 10

The voltage multiplying circuit of claim 7 wherein said first, second and third MOS transistors are of a P-channel type, and said fourth transistor is of an N-channel type.

Claim 11

The voltage multiplying circuit of claim 8 wherein said first and second clock signals are of opposite polarity.

Claim 14

The method of claim 10 wherein said step of charging comprises the step of coupling said first plate of said first capacitor to the primary voltage source and a second plate of said first capacitor to ground to charge said first plate to a voltage level of the primary voltage source.

Claim 15

The method of claim 11 wherein said step of discharging comprises a steps of substantially shorting a first and a second plate of said second capacitor.

Claim 16

The method claim 12 wherein said step of bootstrapping comprises a step of coupling said second plate of said first capacitor to the primary voltage source to bootstrap a voltage level on said first plate of said first capacitor toward twice said voltage level of the primary voltage supply.

Claim 17

The method of claim 13 wherein said step of dividing comprises a step of coupling said second capacitor in parallel with said first capacitor to cause a charge sharing between said first and second capacitors.

Claim 18

The method of claim 14 further comprising a step of repeating said first clock phase and said second clock phase.