US4797899A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated dual charge pump power supply including power down feature and rs-232 transmitter/receiver
Assignee: Maxim Integrated Products Inc
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Filing: 1986-12-15
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Granted: 1989-01-10
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Expires: 2006-12-15
Abstract
Abstract A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.
Inventors
- 👤 Roger W. Fuller
- 👤 David Bingham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:35
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205; G11; G11C; G11C5/00; G11C5/14; G11C5/145; H02M1/00; H02M1/0083; H02M1/009
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
377 words
A circuit, integrateable on a single piece of semiconductor substrate material, for providing a bipolar voltage output at substantially double the voltage of a unipolar voltage input source, including: first and second voltage input terminals, first and second positive transfer capacitor connection terminals, a first set of semiconductor switches for selectively connecting said first voltage input terminal to said first positive transfer capacitor connection terminal and said second voltage input terminal to said second positive transfer capacitor connection terminal, first and second positive reservoir capacitor connection terminals, said first positive reservoir capacitor connection terminal connected to said second voltaqe input terminal, a second set of semiconductor switches for selectively connecting said first voltage input terminal to said second positive transfer capacitor connection terminal and said first positive transfer capacitor connection terminal to said second positive reservoir capacitor connection terminal, first and second negative transfer capacitor connection terminals, a third set of semiconductor switches for selectively connecting said first positive reservoir capacitor connection terminal to said first negative transfer capacitor connection terminal and said second positive reservoir capacitor connection terminal to said second negative transfer capacitor connection terminal, first and second negative reservoir capacitor connection terminals, said first negative reservoir capacitor connection terminal connected to said first positive reservoir capacitor connection terminal, a fourth set of semiconductor switches for selectively connecting said first negative transfer capacitor connection terminal to said second negative reservoir capacitor connection terminal and said second negative transfer capacitor connection terminal to said first negative reservoir capacitor connection terminal, selection circuitry for selectively activating said first, second, third and fourth sets of semiconductor switches, means for clamping said second positive reservoir capacitor connection terminal to a voltage approximately equal to the voltage appearing on said first voltage input terminal, means for clamping said second negative reservoir capacitor connection terminal to a voltage approximately equal to the voltage appearing on said second voltage input terminal, means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material, and means for selectively deactivating said selection circuitry such that selected ones of said first, second, third and fourth sets of semiconductor switches remain on while the remainder of said semiconductor switches remain off.
Claim 2
Dependent Claim
377 words
A circuit, integrateable on a single piece of semiconductor substrate material, for providing a bipolar voltage output at substantially double the voltage of a unipolar voltage input source, including: first and second voltage input terminals, first and second positive transfer capacitor connection terminals, a first set of semiconductor switches for selectively connecting said first voltage input terminal to said first positive transfer capacitor connection terminal and said second voltage input terminal to said second positive transfer capacitor connection terminal, first and second positive reservoir capacitor connection terminals, said first positive reservoir capacitor connection terminal connected to said second voltaqe input terminal, a second set of semiconductor switches for selectively connecting said first voltage input terminal to said second positive transfer capacitor connection terminal and said first positive transfer capacitor connection terminal to said second positive reservoir capacitor connection terminal, first and second negative transfer capacitor connection terminals, a third set of semiconductor switches for selectively connecting said first positive reservoir capacitor connection terminal to said first negative transfer capacitor connection terminal and said second positive reservoir capacitor connection terminal to said second negative transfer capacitor connection terminal, first and second negative reservoir capacitor connection terminals, said first negative reservoir capacitor connection terminal connected to said first positive reservoir capacitor connection terminal, a fourth set of semiconductor switches for selectively connecting said first negative transfer capacitor connection terminal to said second negative reservoir capacitor connection terminal and said second negative transfer capacitor connection terminal to said first negative reservoir capacitor connection terminal, selection circuitry for selectively activating said first, second, third and fourth sets of semiconductor switches, means for clamping said second positive reservoir capacitor connection terminal to a voltage approximately equal to the voltage appearing on said first voltage input terminal, means for clamping said second negative reservoir capacitor connection terminal to a voltage approximately equal to the voltage appearing on said second voltage input terminal, means for inhibiting latch-up of forward biased four layer devices created as a result of layout of said circuit on a single piece of semiconductor substrate material, and means for selectively deactivating said selection circuitry such that selected ones of said first, second, third and fourth sets of semiconductor switches remain on while the remainder of said semiconductor switches remain off.
Claim 3
Dependent Claim
49 words
The circuit of claim 1 further including means for selectively creating a low impedance current path between said first positive reservoir capacitor connection terminal and said second positive reservoir capacitor connection terminal and between said first negative reservoir capacitor connection terminal and said second negative reservoir capacitor connection terminal.
Claim 4
Dependent Claim
54 words
The circuit of claim 1 wherein said means for clamping said negative reservoir capacitor includes a lateral NPN transistor fabricated in said semiconductor substrate material having its lateral collector and base connected to said second negative reservoir capacitor connection terminal and having its vertical collector connected to said second positive reservoir capacitor connection terminal.
Claim 5
Dependent Claim
50 words
The circuit of claim 1 wherein the means for inhibiting latch-up of forward biased four layer devices includes at least one extra collector region of a PNP transistor portion of said four layer device, said collector region disposed an area of the semiconductor substrate material to collect injected minority carriers.
Claim 6
Dependent Claim
126 words
The circuit of claim 1 further including: a plurality of RS-232 transmitter circuits, disposed in said semiconductor substrate material, each having positive, negative and ground potential power conductors connected to said second positive reservoir capacitor terminal, said second negative reservoir capacitor connection terminal, and said first positive reservoir capacitor terminal, respectively, and each having a data input connection terminal connected to said transmitter circuit for providing data to said transmitter, and a data output terminal connection for providing an output from said transmitter, a plurality of RS-232 receiver circuits disposed on said semiconductor substrate material, each including ositive. and ground power connection terminals connected to said first and second voltage input terminals and each having a data input connection terminal and a data output connection terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-10 | 1992-07-11 | 1993-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-10 | 1996-07-11 | 1997-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-10 | 2000-07-11 | 2001-01-10 | $7700.00 | Window Closed / Lapsed |