Eliminating metal extrusions by controlling the liner deposition temperature

Claim 1

An integrated circuit manufacturing process for forming on a surface of a silicon substrate an interlevel dielectric (ILD) atop a first patterned metal layer, said ILD separating said first metal from a second metal layer to be deposited upon said ILD, comprising the steps of: providing a silicon substrate having a device therein at said surface, said substrate having a first patterned metal layer thereon comprising metal lines separated by gaps; depositing a first conformal liner dielectric layer onto said first patterned metal layer at a first deposition temperature, thereby inducing stress in said metal lines of said first patterned metal layer; depositing a second dielectric layer onto said liner layer at a second temperature lower than said first temperature, to substantially fill said gaps between said metal lines; etching a via hole through said first and second dielectric layers to contact one of said metal lines; after said etching step, degassing said wafer at a degassing temperature lower than or equal to said first deposition temperature; and filling said via hole with a conducting material at a third temperature lower than said first deposition temperature, said stress in said metal lines being in a non-compressive stress state at all times.