US5789312A
Expired / Lapsed
US
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Method of fabricating mid-gap metal gates compatible with ultra-thin dielectrics
Assignee: GlobalFoundries Inc
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Filing: 1996-10-30
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Granted: 1998-08-04
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Expires: 2016-10-30
Abstract
Abstract A method of fabricating a mid-gap workfunction tungsten gate or W electrode directly onto a gate dielectric material for use in high speed/high density advanced MOS and CMOS devices is provided which utilizes low temperature/low pressure CVD of a tungsten carbonyl. MOS and CMOS devices containing one or more of the CVD W gates or W electrodes manufactured by the present invention are also provided herein.
Inventors
- 👤 Douglas Andrew Buchanan
- 👤 Fenton Read McFeely
- 👤 John Jacob Yurkas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:25
CPC Classifications
C; C23; C23C; C23C16/00; C23C16/06; C23C16/16; H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01316; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/60; H10D64/66; H10D64/665; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/42; H10P14/43
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
89 words
A method of fabricating a mid-gap workfunction tungsten (W) gate for use in metal oxide semiconductor (MOS) applications, said method comprises (a) depositing a layer of W onto a gate dielectric material, said gate dielectric material being positioned on a semiconductor substrate, wherein said depositing step is carried out by chemical vapor deposition (CVD) using W(CO) 6 as a source material; and (b) patterning the structure formed in step (a) using lithographic techniques to form a MOS device containing said mid-gap workfunction W gate on said gate dielectric material.
Claim 2
Independent Claim
89 words
A method of fabricating a mid-gap workfunction tungsten (W) gate for use in metal oxide semiconductor (MOS) applications, said method comprises (a) depositing a layer of W onto a gate dielectric material, said gate dielectric material being positioned on a semiconductor substrate, wherein said depositing step is carried out by chemical vapor deposition (CVD) using W(CO) 6 as a source material; and (b) patterning the structure formed in step (a) using lithographic techniques to form a MOS device containing said mid-gap workfunction W gate on said gate dielectric material.
Claim 3
Dependent Claim
25 words
The method of claim 1 wherein said gate dielectric material is an ultra-thin gate dielectric material having a thickness of less than about 4.0 nm.
Claim 4
Dependent Claim
20 words
The method of claim 2 wherein said ultra-thin gate dielectric material has a thickness of less than about 3 nm.
Claim 5
Dependent Claim
35 words
The method of claim 3 wherein said ultra-thin gate dielectric material is selected from the group consisting of SiO 2 , nitrided SiO 2 , Si 3 N 4 , metal oxides and mixtures thereof.
Claim 6
Dependent Claim
15 words
The method of claim 4 wherein said ultra-thin gate dielectric material is SiO 2 .
Claim 7
Dependent Claim
20 words
The method of claim 1 wherein said semiconductor substrate contains at least one source and at least one drain region.
Claim 8
Dependent Claim
17 words
The method of claim 6 wherein said semiconductor substrate is of the p-type or of the n-type.
Claim 9
Dependent Claim
18 words
The method of claim 7 wherein said semiconductor substrate is a substrate composed of silicon, SiGe or GaAs.
Claim 10
Dependent Claim
13 words
The method of claim 8 wherein said semiconductor substrate is composed of silicon.
Claim 11
Dependent Claim
23 words
The method of claim 1 wherein said CVD is carried out at a temperature of from about 250° C. to about 500° C.
Claim 12
Dependent Claim
23 words
The method of claim 10 wherein said CVD is carried out at a temperature of from about 275° C. to about 600° C.
Claim 13
Dependent Claim
24 words
The method of claim 1 wherein said CVD is carried out at a pressure of about 1×10 -6 Torr to about 3×10 -4 Torr.
Claim 14
Dependent Claim
24 words
The method of claim 12 wherein said CVD is carried out at a pressure of about 1×10 -4 Torr to about 2×10 -4 Torr.
Claim 15
Dependent Claim
25 words
The method of claim 1 wherein said CVD results in said W layer having a thickness of from about 3.5 nm to about 200 nm.
Claim 16
Dependent Claim
18 words
The method of claim 14 wherein said W thickness is from about 50 nm to about 100 nm.
Claim 17
Dependent Claim
36 words
The method of claim 1 wherein said patterning step comprises positioning at least one photoresist on an area of said W layer; developing said photoresist; and etching areas of said W layer not containing said photoresist.
Claim 18
Dependent Claim
15 words
The method of claim 16 wherein said etching step comprises wet etching or dry etching.
Claim 19
Dependent Claim
35 words
The method of claim 17 wherein said wet etching is conducted using a chemical etchant selected from the group consisting of H 2 O 2 , phosphoric acid, chromic acid, nitric acid, and mixtures thereof.
Claim 20
Dependent Claim
15 words
The method of claim 18 wherein said chemical etchant is H 2 O 2 .
Claim 21
Dependent Claim
21 words
The method of claim 17 wherein said dry etching includes Reactive Ion Etching (RIE), Ion Beaming Etching (IBE) and Laser Ablation.
Claim 22
Dependent Claim
32 words
The method of claim 1 wherein said semiconductor substrate is a p-type or n-type semiconductor substrate of a MOS wafer, said MOS wafer having at least one source and drain region therein.
Claim 23
Independent Claim
51 words
A method of fabricating a tungsten (W) electrode comprising the steps of: (a) depositing a layer of W onto a dielectric material, wherein said depositing comprises chemical vapor deposition using W(CO) 6 as a source material; and (b) patterning said W layer to form said W electrode on said dielectric material.
Claim 24
Independent Claim
51 words
A method of fabricating a tungsten (W) electrode comprising the steps of: (a) depositing a layer of W onto a dielectric material, wherein said depositing comprises chemical vapor deposition using W(CO) 6 as a source material; and (b) patterning said W layer to form said W electrode on said dielectric material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |