US5789290A
Expired / Lapsed
US
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Polysilicon CMP process for high-density DRAM cell structures
Assignee: United Microelectronics Corp
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Filing: 1997-02-26
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Granted: 1998-08-04
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Expires: 2017-02-26
Abstract
Abstract Pass transistors are formed on the active device regions of a substrate and a layer of silicon oxide is deposited over the transistors and the surface of the layer of silicon oxide is planarized. A thin layer of silicon nitride is deposited on the oxide layer and then vias are opened through the silicon nitride and silicon oxide layers to expose one of the source/drain regions of each of the pass transistors in the memory array. A layer of polysilicon is deposited so as to extend through the vias, forming polysilicon vertical interconnects in contact with the source/drain regions of the pass transistors and then the layer of polysilicon is patterned to form capacitor bottom plates, with each of the capacitor bottom plates connected to a corresponding source/drain region. A second layer of silicon oxide is deposited to cover the capacitor bottom plates and photolithography is performed to provide a plurality of openings through the second silicon oxide layer to each of the capacitor bottom plates. Polysilicon is deposited to fill each of the openings and chemical mechanical polishing is performed to remove excess polysilicon using the silicon oxide layer as a polish stop. The second oxide layer is stripped to leave the capacitor bottom plates with fins or posts extending vertically from the bottom plates. A capacitor dielectric is then formed over the capacitor bottom electrodes, capacitor upper electrodes are formed, and further processing continues in the conventional manner.
Inventors
- 👤 Shih-Wei Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:50
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
238 words
A method of making a memory device on a substrate, the memory device including a charge storage capacitor, the method comprising the steps of: providing a transistor having source/drain regions formed on a surface of the substrate, and having a gate electrode formed above the surface of the substrate; depositing a first insulating layer over the transistor; depositing over the first insulating layer a second insulating layer of an insulating material different from the first insulating layer; providing a first opening through the first and second insulating layers to expose a first source/drain region of the transistor; depositing a first layer of polysilicon over the second insulating layer, the first layer of polysilicon in electrical contact with the first source/drain region of the transistor; depositing a third insulating layer over the first layer of polysilicon and patterning the third insulating layer to provide second openings and to expose the first layer of polysilicon; depositing a second layer of polysilicon to fill the second openings; polishing to remove excess portions of the second layer of polysilicon; removing the third insulating layer to expose a polysilicon superstructure extending vertically above the first layer of polysilicon, forming at least a part of a bottom electrode for the charge storage capacitor; forming a dielectric layer over the polysilicon superstructure and the first layer of polysilicon; and depositing a third layer of polysilicon and forming an upper electrode for the charge storage capacitor.
Claim 2
Independent Claim
238 words
A method of making a memory device on a substrate, the memory device including a charge storage capacitor, the method comprising the steps of: providing a transistor having source/drain regions formed on a surface of the substrate, and having a gate electrode formed above the surface of the substrate; depositing a first insulating layer over the transistor; depositing over the first insulating layer a second insulating layer of an insulating material different from the first insulating layer; providing a first opening through the first and second insulating layers to expose a first source/drain region of the transistor; depositing a first layer of polysilicon over the second insulating layer, the first layer of polysilicon in electrical contact with the first source/drain region of the transistor; depositing a third insulating layer over the first layer of polysilicon and patterning the third insulating layer to provide second openings and to expose the first layer of polysilicon; depositing a second layer of polysilicon to fill the second openings; polishing to remove excess portions of the second layer of polysilicon; removing the third insulating layer to expose a polysilicon superstructure extending vertically above the first layer of polysilicon, forming at least a part of a bottom electrode for the charge storage capacitor; forming a dielectric layer over the polysilicon superstructure and the first layer of polysilicon; and depositing a third layer of polysilicon and forming an upper electrode for the charge storage capacitor.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein one of the first and the second insulating layer comprises silicon oxide and another of the first and second insulating layer comprises silicon nitride.
Claim 4
Dependent Claim
13 words
The method of claim 2, wherein the first insulating layer is silicon oxide.
Claim 5
Dependent Claim
18 words
The method of claim 1, further comprising the step of planarizing the surface of the first insulating layer.
Claim 6
Dependent Claim
17 words
The method of claim 1, wherein the first opening is filled by the first layer of polysilicon.
Claim 7
Dependent Claim
21 words
The method of claim 1, wherein the third insulating layer is removed using the second insulating layer as an etch stop.
Claim 8
Dependent Claim
13 words
The method of claim 5, wherein the third insulating layer is silicon oxide.
Claim 9
Dependent Claim
38 words
The method of claim 7, further comprising the step, prior to the step of depositing a third insulating layer, of patterning the first layer of polysilicon to form a plate above the first source/drain region of the transistor.
Claim 10
Dependent Claim
22 words
The method of claim 1, wherein the transistor is coupled to a bit line and wherein the memory device is a DRAM.
Claim 11
Dependent Claim
29 words
The method of claim 1, wherein the step of polishing is a chemical mechanical polishing process that uses a surface of the third insulating layer as a polish stop.
Claim 12
Dependent Claim
16 words
The method of claim 1, wherein the polysilicon superstructure comprises an array of fins or posts.
Claim 13
Independent Claim
221 words
A method of making a memory device on a substrate, the memory device including a charge storage capacitor, the method comprising the steps of: providing a transistor having source/drain regions formed on a surface of the substrate, and having a gate electrode formed above the surface of the substrate; depositing a first insulating layer over the transistor; providing a first opening through the first insulating layer to expose a first source/drain region of the transistor; forming a first layer of conductive material over the first insulating layer, the first layer of conductive material electrically coupled to the first source/drain region of the transistor; depositing a second insulating layer over the first layer of conductive material and patterning the second insulating layer to provide second openings which expose the first layer of conductive material; depositing a second layer of conductive material to fill the second openings; polishing to remove excess portions of the second layer of conductive material; removing the second insulating layer to expose a superstructure extending vertically above the first layer of conductive material, forming at least a part of a bottom electrode for the charge storage capacitor; forming a dielectric layer over the superstructure and the first layer of conductive material, and depositing a third layer of conductive material and forming an upper electrode for the charge storage capacitor.
Claim 14
Independent Claim
221 words
A method of making a memory device on a substrate, the memory device including a charge storage capacitor, the method comprising the steps of: providing a transistor having source/drain regions formed on a surface of the substrate, and having a gate electrode formed above the surface of the substrate; depositing a first insulating layer over the transistor; providing a first opening through the first insulating layer to expose a first source/drain region of the transistor; forming a first layer of conductive material over the first insulating layer, the first layer of conductive material electrically coupled to the first source/drain region of the transistor; depositing a second insulating layer over the first layer of conductive material and patterning the second insulating layer to provide second openings which expose the first layer of conductive material; depositing a second layer of conductive material to fill the second openings; polishing to remove excess portions of the second layer of conductive material; removing the second insulating layer to expose a superstructure extending vertically above the first layer of conductive material, forming at least a part of a bottom electrode for the charge storage capacitor; forming a dielectric layer over the superstructure and the first layer of conductive material, and depositing a third layer of conductive material and forming an upper electrode for the charge storage capacitor.
Claim 15
Dependent Claim
29 words
The method of claim 12, wherein the step of polishing is a chemical mechanical polishing process that uses a surface of the second insulating layer as a polish stop.
Claim 16
Dependent Claim
26 words
The method of claim 12, wherein the second insulating layer is formed from a material different from the material used to form the first insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |