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US5784394A
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Method and system for implementing parity error recovery schemes in a data processing system
Assignee: International Business Machines Corp
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Filing: 1996-11-15
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Granted: 1998-07-21
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Expires: 2016-11-15
Abstract
Abstract A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.
Inventors
- 👤 II Manuel Joseph Alvarez
- 👤 Gary Dale Carpenter
- 👤 Kai Cheng
- 👤 Jeffrey Holland Gruger
- 👤 Jin Chin Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:03
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/082; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076; G06F11/108
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
163 words
In a data processing system having a plurality of node controllers and a memory unit for each one of the node controllers, each one of the node controllers having at least one processor having a cache, each memory unit including a plurality of entries each having an exclusive bit, an address tag, an inclusion field, a first parity error bit, and a second parity error bit, each bit of the inclusion field representing one of the node controllers, a method of detecting errors in each of the entries, the method comprising the steps of: selecting the exclusive bit and a portion of the address tag for error detection using the first parity bit; selecting the remaining portion of the address tag and inclusion field for error detection using the second parity bit; detecting an error in one of the entries with the first and/or second parity bit; and flushing the cache lines of the processors having data represented by the entry in error.
Claim 2
Dependent Claim
163 words
In a data processing system having a plurality of node controllers and a memory unit for each one of the node controllers, each one of the node controllers having at least one processor having a cache, each memory unit including a plurality of entries each having an exclusive bit, an address tag, an inclusion field, a first parity error bit, and a second parity error bit, each bit of the inclusion field representing one of the node controllers, a method of detecting errors in each of the entries, the method comprising the steps of: selecting the exclusive bit and a portion of the address tag for error detection using the first parity bit; selecting the remaining portion of the address tag and inclusion field for error detection using the second parity bit; detecting an error in one of the entries with the first and/or second parity bit; and flushing the cache lines of the processors having data represented by the entry in error.
Claim 3
Dependent Claim
29 words
The method of claim 1 wherein the step of detecting an error includes the step of: detecting an error in one of the entries with the first parity bit.
Claim 4
Dependent Claim
50 words
The method of claim 2 wherein the step of flushing includes the steps of: generating the address represented by the entry in error; and instructing the node controllers identified by the bits of the inclusion field of the entry in error to flush any cache lines having the generated address.
Claim 5
Dependent Claim
29 words
The method of claim 3 wherein the step of detecting an error includes the step of: detecting an error in one of the entries with the second parity bit.
Claim 6
Dependent Claim
39 words
The method of claim 4 wherein the step of flushing includes the steps of: generating the address represented by the entry in error; and instructing all of the node controllers to flush all cache lines having the generated address.
Claim 7
Dependent Claim
29 words
The method of claim 1 wherein the step of detecting an error includes the step of: detecting an error in one of the entries with the second parity bit.
Claim 8
Dependent Claim
39 words
The method of claim 6 wherein the step of flushing includes the steps of: generating the address represented by the entry in error; and instructing all of the node controllers to flush all cache lines having the generated address.
Claim 9
Dependent Claim
168 words
In a data processing system having a plurality of node controllers and a memory unit for each one of the node controllers, each one of the node controllers having at least one processor having a cache, each memory unit including a plurality of entries each having an exclusive bit, an address tag, an inclusion field, a first parity error bit, and a second parity error bit, each bit of the inclusion field representing one of the node controllers, an apparatus for detecting errors in each of the entries, the apparatus comprising: means for selecting the exclusive bit and a portion of the address tag for error detection using the first parity bit; means for selecting the remaining portion of the address tag and inclusion field for error detection using the second parity bit; means for detecting an error in one of the entries with the first and/or second parity bit; and means for flushing the cache lines of the processors having data represented by the entry in error.
Claim 10
Dependent Claim
168 words
In a data processing system having a plurality of node controllers and a memory unit for each one of the node controllers, each one of the node controllers having at least one processor having a cache, each memory unit including a plurality of entries each having an exclusive bit, an address tag, an inclusion field, a first parity error bit, and a second parity error bit, each bit of the inclusion field representing one of the node controllers, an apparatus for detecting errors in each of the entries, the apparatus comprising: means for selecting the exclusive bit and a portion of the address tag for error detection using the first parity bit; means for selecting the remaining portion of the address tag and inclusion field for error detection using the second parity bit; means for detecting an error in one of the entries with the first and/or second parity bit; and means for flushing the cache lines of the processors having data represented by the entry in error.
Claim 11
Dependent Claim
28 words
The apparatus of claim 8 wherein the means for detecting an error includes: means for detecting an error in one of the entries with the first parity bit.
Claim 12
Dependent Claim
51 words
The apparatus of claim 9 wherein the means for flushing includes: means for generating the address represented by the entry in error; and means for instructing the node controllers identified by the bits of the inclusion field of the entry in error to flush any cache lines having the generated address.
Claim 13
Dependent Claim
28 words
The apparatus of claim 10 wherein the means for detecting an error includes: means for detecting an error in one of the entries with the second parity bit.
Claim 14
Dependent Claim
40 words
The apparatus of claim 11 wherein the means for flushing includes: means for generating the address represented by the entry in error; and means for instructing all of the node controllers to flush all cache lines having the generated address.
Claim 15
Dependent Claim
28 words
The apparatus of claim 9 wherein the means for detecting an error includes: means for detecting an error in one of the entries with the second parity bit.
Claim 16
Dependent Claim
40 words
The apparatus of claim 13 wherein the means for flushing includes: means for generating the address represented by the entry in error; and means for instructing all of the node controllers to flush all cache lines having the generated address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-20 | 2002-01-19 | 2002-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-20 | 2006-01-19 | 2006-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-20 | 2010-01-19 | 2010-07-21 | $7700.00 | Window Closed / Lapsed |