US5780900A
Expired / Lapsed
US
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Thin film silicon-on-insulator transistor having an improved power dissipation, a high break down voltage, and a low on resistance
Assignee: Panasonic Electric Works Co Ltd
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Filing: 1996-10-17
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Granted: 1998-07-14
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Expires: 2016-10-17
Abstract
Abstract A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first conductive type formed on the buried oxide layer, and an upper oxide layer formed on the silicon layer. The silicon layer has a body region of a second conductive type, source region of the first conductive type, drain region of the first conductive type, and a drift region of the first conductive type. The silicon layer is formed with a first portion of a thickness T1 in which the doping region is formed, and a second portion of a thickness T2 in which the body region is formed to reach the buried oxide layer. When the thicknesses T1 and T2 are determined so as to satisfy the relationships: 0.4 μm<T1, 0.4 μm≦T2≦1.5 μm, and T2<T1, The transistor exhibits an improved power dissipation, high breakdown voltage, and a low on-resistance, and also provides advantages in a manufacturing process of the transistor.
Inventors
- 👤 Yuji Suzuki
- 👤 Hitomichi Takano
- 👤 Masahiko Suzumura
- 👤 Yoshiki Hayasaki
- 👤 Takashi Kishida
- 👤 Yoshifumi Shirai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D30/657; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/10; H10D62/117; H10D62/157; H10D64/00; H10D64/111
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
255 words
A thin film transistor of silicon-on-insulator type comprising: a buried oxide layer formed on a semiconductor substrate; a silicon layer of a first conductive type formed on said buried oxide layer, said silicon layer having a body region of a second conductive type, source region of said first conductive type, drain region of said first conductive type, and a drift region of said first conductive type formed between said source and drain regions, said source region being formed in said body region to be spaced from said buried oxide layer, and said drift region being formed with a lateral linear doping region; an upper oxide layer formed on said silicon layer; a source electrode contacting both of said body region and said source region; a drain electrode contacting said drain region; and a gate electrode disposed between said source and drain electrodes and spaced from said silicon layer by a thin oxide layer, said gate electrode having a field plate which is short-circuited to said gate electrode, and said gate electrode and field plate extending laterally in a spaced relation from said silicon layer without overlying said linear doping region, wherein said silicon layer is formed with a first portion of a thickness (T1) in which said drift region is formed, and a second portion of a thickness (T2) in which said body region is formed to reach said buried oxide layer, and wherein said thicknesses (T1) and (T2) are determined so as to satisfy the following relationships: 0.4 μm<T1 0.4 μm≦T2≦1.5 μm T2<T1. 2.
Claim 2
Dependent Claim
255 words
A thin film transistor of silicon-on-insulator type comprising: a buried oxide layer formed on a semiconductor substrate; a silicon layer of a first conductive type formed on said buried oxide layer, said silicon layer having a body region of a second conductive type, source region of said first conductive type, drain region of said first conductive type, and a drift region of said first conductive type formed between said source and drain regions, said source region being formed in said body region to be spaced from said buried oxide layer, and said drift region being formed with a lateral linear doping region; an upper oxide layer formed on said silicon layer; a source electrode contacting both of said body region and said source region; a drain electrode contacting said drain region; and a gate electrode disposed between said source and drain electrodes and spaced from said silicon layer by a thin oxide layer, said gate electrode having a field plate which is short-circuited to said gate electrode, and said gate electrode and field plate extending laterally in a spaced relation from said silicon layer without overlying said linear doping region, wherein said silicon layer is formed with a first portion of a thickness (T1) in which said drift region is formed, and a second portion of a thickness (T2) in which said body region is formed to reach said buried oxide layer, and wherein said thicknesses (T1) and (T2) are determined so as to satisfy the following relationships: 0.4 μm<T1 0.4 μm≦T2≦1.5 μm T2<T1. 2.
Claim 3
Dependent Claim
22 words
A thin film transistor as set forth in claim 1, wherein said first and second conductive types are n-type and p-type, respectively.
Claim 4
Dependent Claim
19 words
A thin film transistor as set forth in claim 1, wherein said thickness (T1) is 1 μm or more.
Claim 5
Dependent Claim
28 words
A thin film transistor as set forth in claim 1, wherein said drain region is formed in said silicon layer to be spaced from said buried oxide layer.
Claim 6
Dependent Claim
269 words
A thin film transistor of silicon-on-insulator type comprising: a buried oxide layer formed on a semiconductor substrate; a silicon layer of a first conductive type formed on said buried oxide layer, said silicon layer having a body region of a second conductive type, source region of said first conductive type, drain region of said first conductive type, and a drift region of said first conductive type formed between said source and drain regions, said source region being formed in said body region to be spaced from said buried oxide layer; an upper oxide layer formed on said silicon layer; a source electrode contacting both of said body region and said source region; a drain electrode contacting said drain region; and a gate electrode disposed between said source and drain electrodes and spaced from said silicon layer by a thin oxide layer; wherein said silicon layer is formed with a first portion of a thickness (T1) in which said drift region is formed, and a second portion of a thickness (T2) in which said body region is formed to reach said buried oxide layer, said thicknesses (T1) and (T2) being determined so as to satisfy the following relationships: 0.4 μm<T1 0.4 μm≦T2≦1.5 μm T2<T1; and wherein said silicon layer is formed on its upper surface with a slope extending from said second portion to said first portion, said body region extending along said slope from said second portion toward said first portion, and said gate electrode having a field plate which extends in parallel with said slope and in a spaced relation from said slope by said thin oxide layer.
Claim 7
Dependent Claim
269 words
A thin film transistor of silicon-on-insulator type comprising: a buried oxide layer formed on a semiconductor substrate; a silicon layer of a first conductive type formed on said buried oxide layer, said silicon layer having a body region of a second conductive type, source region of said first conductive type, drain region of said first conductive type, and a drift region of said first conductive type formed between said source and drain regions, said source region being formed in said body region to be spaced from said buried oxide layer; an upper oxide layer formed on said silicon layer; a source electrode contacting both of said body region and said source region; a drain electrode contacting said drain region; and a gate electrode disposed between said source and drain electrodes and spaced from said silicon layer by a thin oxide layer; wherein said silicon layer is formed with a first portion of a thickness (T1) in which said drift region is formed, and a second portion of a thickness (T2) in which said body region is formed to reach said buried oxide layer, said thicknesses (T1) and (T2) being determined so as to satisfy the following relationships: 0.4 μm<T1 0.4 μm≦T2≦1.5 μm T2<T1; and wherein said silicon layer is formed on its upper surface with a slope extending from said second portion to said first portion, said body region extending along said slope from said second portion toward said first portion, and said gate electrode having a field plate which extends in parallel with said slope and in a spaced relation from said slope by said thin oxide layer.
Claim 8
Dependent Claim
22 words
A thin film transistor as set forth in claim 5, wherein said first and second conductive types are n-type and p-type, respectively.
Claim 9
Dependent Claim
22 words
A thin film transistor as set forth in claim 5, wherein said drift region is formed with a lateral linear doping region.
Claim 10
Dependent Claim
19 words
A thin film transistor as set forth in claim 5, wherein said thickness (TI) is 1 μm or more.
Claim 11
Dependent Claim
28 words
A thin film transistor as set forth in claim 5, wherein said drain region is formed in said silicon layer to be spaced from said buried oxide layer.
References Cited (Backward Citations)
US4922327A
Cited
US5246870A
Cited
US5300448A
Cited
US5362979A
Cited
US5338965A
Cited
US5548150A
Cited
US5378912A
Cited
US5510275A
Cited
US5382818A
Cited
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