US5780333A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating an analog semiconductor device having a salicide layer
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1997-06-26
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Granted: 1998-07-14
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Expires: 2017-06-26
Abstract
Abstract An analog semiconductor device having a salicide(self-aligned silicide) layer and a method of fabricating the same are disclosed. An isolation layer is formed on a semiconductor substrate to define an active region, and a resistor is formed on the isolation layer. A capacitor insulating layer and dummy upper capacitor electrode are formed on a predetermined portion of the resistor, and a salicide layer is selectively formed on the dummy upper capacitor electrode and exposed portions of the resistor. The dummy upper capacitor electrode and one side of the exposed portion of the resistor are electrically connected to each other, to thereby form the analog semiconductor device.
Inventors
- 👤 Jae-Kap Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:15
CPC Classifications
H; H10; H10B; H10B12/00; H10D; H10D88/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
194 words
A method of fabricating an analog semiconductor device wherein an isolation layer is formed on a semiconductor substrate to define an active region, a resistor is formed on a predetermined portion of the isolation layer, a capacitor insulating layer and dummy upper capacitor electrode are formed on a predetermined portion of the resistor, and a salicide layer is selectively formed on the dummy upper capacitor electrode and exposed portions of the resistor, the method comprising the steps of: forming an intermediate insulating layer on the substrate; etching the intermediate insulating layer, to form first and second contact holes exposing predetermined portions of the salicide layer formed on the resistor, and a third contact hole exposing a predetermined portion of the salicide layer formed on the dummy upper capacitor electrode; forming a conductivity layer on the intermediate insulating layer, to fill the first, second and third contact holes; and patterning the conductivity layer, to form a first interconnection layer electrically connecting the resistor to the dummy capacitor electrode through the first and second contact holes, and second interconnection layer coming into contact with the salicide layer formed on the resistor through the second contact hole.
Claim 2
Independent Claim
194 words
A method of fabricating an analog semiconductor device wherein an isolation layer is formed on a semiconductor substrate to define an active region, a resistor is formed on a predetermined portion of the isolation layer, a capacitor insulating layer and dummy upper capacitor electrode are formed on a predetermined portion of the resistor, and a salicide layer is selectively formed on the dummy upper capacitor electrode and exposed portions of the resistor, the method comprising the steps of: forming an intermediate insulating layer on the substrate; etching the intermediate insulating layer, to form first and second contact holes exposing predetermined portions of the salicide layer formed on the resistor, and a third contact hole exposing a predetermined portion of the salicide layer formed on the dummy upper capacitor electrode; forming a conductivity layer on the intermediate insulating layer, to fill the first, second and third contact holes; and patterning the conductivity layer, to form a first interconnection layer electrically connecting the resistor to the dummy capacitor electrode through the first and second contact holes, and second interconnection layer coming into contact with the salicide layer formed on the resistor through the second contact hole.
Claim 3
Dependent Claim
20 words
The method of fabricating an analog semiconductor device as claimed in claim 1, wherein the resistor is formed of polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-13 | 2002-01-12 | 2002-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-13 | 2006-01-12 | 2006-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-13 | 2010-01-12 | 2010-07-14 | $7700.00 | Window Closed / Lapsed |