US5597759A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a semiconductor integrated circuit device having a capacitor and a resistor
Assignee: NEC Electronics Corp
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Filing: 1995-10-06
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Granted: 1997-01-28
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Expires: 2015-10-06
Abstract
Abstract A semiconductor integrated circuit device includes a capacitor and a resistor in addition to a transistor. The capacitor includes a lower electrode made of a first polysilicon layer formed on an insulating layer covering the main surface of a semiconductor substrate, a dielectric film formed on the lower electrode and a upper electrode formed on the dielectric layer, whereas the resistor includes a resistor layer made of a second polysilicon layer formed on the insulating film. The first polysilicon layer has the same sheet resistance as the second polysilicon layer.
Inventors
- 👤 Masanori Yoshimori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D30/00; H10D30/60; H10D30/67; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
177 words
A method of fabricating a semiconductor integrated circuit device comprising the steps of: selectively forming a field insulation layer on a main surface of a semiconductor substrate to define an active region; forming a first polysilicon layer on said field insulation layer and said active region; forming a dielectric layer having at least one oxide layer and a nitride layer on said first polysilicon layer; patterning said dielectric layer and said first polysilicon layer to form a lower electrode of a capacitor made of said first polysilicon layer and a dielectric film of said capacitor made of said dielectric layer; forming a second polysilicon layer on at least said dielectric film and said active region after the step of pattering said dielectric layer and said first polysilicon layer; and patterning said second polysilicon layer to form an upper electrode of said capacitor and a gate electrode formed on said active region, whereby said upper electrode of said capacitor and said gate electrode are formed after the step of pattering said dielectric layer and said first polysilicon layer.
Claim 2
Independent Claim
177 words
A method of fabricating a semiconductor integrated circuit device comprising the steps of: selectively forming a field insulation layer on a main surface of a semiconductor substrate to define an active region; forming a first polysilicon layer on said field insulation layer and said active region; forming a dielectric layer having at least one oxide layer and a nitride layer on said first polysilicon layer; patterning said dielectric layer and said first polysilicon layer to form a lower electrode of a capacitor made of said first polysilicon layer and a dielectric film of said capacitor made of said dielectric layer; forming a second polysilicon layer on at least said dielectric film and said active region after the step of pattering said dielectric layer and said first polysilicon layer; and patterning said second polysilicon layer to form an upper electrode of said capacitor and a gate electrode formed on said active region, whereby said upper electrode of said capacitor and said gate electrode are formed after the step of pattering said dielectric layer and said first polysilicon layer.
Claim 3
Dependent Claim
70 words
The method as claimed in claim 1, wherein said at least one oxide layer comprises a lower oxide layer and an upper oxide layer and said step of forming said dielectric layer comprises the steps of forming said lower oxide layer by oxidizing a surface of said first polysilicon layer, depositing said nitride layer on said lower oxide layer, and forming said upper oxide layer by oxidizing said nitride layer.
Claim 4
Dependent Claim
32 words
The method as claimed in claim 2, wherein said lower oxide layer and said upper oxide layer are each silicon oxide layers and wherein said nitride layer is a silicon nitride layer.
Claim 5
Dependent Claim
39 words
The method as claimed in claim 1, wherein said dielectric layer and said first polysilicon layer patterning step also forms a resistor layer from said patterned first polysilicon layer and a protective insulating film from said patterned dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |