DRAM with high bandwidth interface that uses packets and arbitration

Claim 2

A memory chip, comprising: a memory array that decodes, arbitrates between, and executes memory array access commands, and for generates memory array access responses; and a high bandwidth data interface, coupled with the memory array, comprising; a data path, an interface controller, and a packet buffer, said data path is coupled with the packet buffer and interface controller, and receives an input data stream through an input port and transmits an output data stream through an output port, said interface controller is coupled with the packet buffer, and controls flow of the input and output data streams within the memory chip, and said packet buffer is coupled between the data path and the memory array, and temporarily stores data from the input and output data streams, and includes a data path through a forward queue that directly links the input port to the output for forwarding data through the packet buffer without being processed by the interface controller or memory array.

Claim 3

The memory chip of claim 1, wherein the memory array comprises a dynamic random access memory array coupled with a memory array controller.

Claim 4

The memory chip of claim 1, wherein the memory array comprises a static random access memory array coupled with a memory array controller.

Claim 5

The memory chip of claim 1, wherein the memory array includes an error circuit that performs single-bit error detection and correction.

Claim 6

The memory chip of claim 1, wherein the data path comprises an input port having a plurality of input receivers configured in parallel and an output port having a plurality of output drivers configured in parallel.

Claim 7

The memory chip of claim 1, wherein the interface controller comprises: a receiver section having a receive control circuit coupled with the data path and the packet buffer, and a request queue coupled between the receive control circuit, the packet buffer and the memory array; and a transmitter section having a transmit control circuit coupled with the packet buffer, and a response queue coupled between the transmit control circuit, the packet buffer and the memory array.

Claim 8

The memory chip of claim 1, wherein the packet buffer comprises a static random access memory.

Claim 9

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates, comprising: a memory array, coupled with a memory array controller, that decodes, arbitrates between, and executes memory array access commands, and generates memory array access responses; and a high bandwidth data interface, coupled with the memory array and the memory array controller, comprising; a unidirectional input port, a unidirectional output port, a packet buffer, and an interface controller that includes a receiver section and a transmitter section, said unidirectional input port is coupled with the packet buffer and the receiver section, and receives an input data stream comprising memory array access commands, forwarding data and an input clock signal, said unidirectional output port is coupled with the packet buffer and the transmitter section, and transmits an output data stream comprising memory array access responses, forwarding data and an output clock signal, said receiver section is coupled with the packet buffer and the memory array controller, and decodes and controls flow of the input data stream from the input port to the packet buffer, and to the memory array and the memory array controller, said transmitter section is coupled with the packet buffer and the memory array controller, and controls flow of the output data stream from the packet buffer to the output port, and said packet buffer is coupled between the input and output ports and the memory array, and stores the memory array access commands prior to servicing by the memory array and the memory array controller, and stores the memory array access responses and the forwarding data prior to servicing by the transmitter section, and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller or memory array.

Claim 10

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates, comprising: a memory array, coupled with a memory array controller, that decodes, arbitrates between, and executes memory array access commands, and generates memory array access responses; and a high bandwidth data interface, coupled with the memory array and the memory array controller, comprising; a unidirectional input port, a unidirectional output port, a packet buffer, and an interface controller that includes a receiver section and a transmitter section, said unidirectional input port is coupled with the packet buffer and the receiver section, and receives an input data stream comprising memory array access commands, forwarding data and an input clock signal, said unidirectional output port is coupled with the packet buffer and the transmitter section, and transmits an output data stream comprising memory array access responses, forwarding data and an output clock signal, said receiver section is coupled with the packet buffer and the memory array controller, and decodes and controls flow of the input data stream from the input port to the packet buffer, and to the memory array and the memory array controller, said transmitter section is coupled with the packet buffer and the memory array controller, and controls flow of the output data stream from the packet buffer to the output port, and said packet buffer is coupled between the input and output ports and the memory array, and stores the memory array access commands prior to servicing by the memory array and the memory array controller, and stores the memory array access responses and the forwarding data prior to servicing by the transmitter section, and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller or memory array.

Claim 11

The memory chip of claim 8, wherein the input port comprises a plurality of input receivers configured in parallel, and the output port comprises a plurality of output drivers configured in parallel.

Claim 12

The memory chip of claim 9, wherein the input port further comprises a demultiplexer coupled with the plurality of input receivers, and the output port further comprises a multiplexer coupled with the plurality of output drivers.

Claim 13

The memory chip of claim 8, wherein; the input port comprises nine input receivers that receive an input clock signal having both rising and falling edges, and receive eight parallel input data signals with said parallel input data signals being clocked on both the rising and falling edges of the input clock signal, said nine input receivers are coupled with an eight-bit to sixteen-bit demultiplexer that converts the eight parallel input data signals to sixteen parallel input data signals clocked only on either the rising or the falling edges of the input clock signal, and the output port comprises a sixteen-bit to eight-bit multiplexer, clocked by an output clock signal having both rising and falling edges, that converts sixteen parallel output data signals clocked only on either the rising or the falling edges of the output clock signal to eight parallel output data signals clocked on both the rising and falling edges of the output clock signal, said sixteen-bit to eight-bit multiplexer is coupled with nine output drivers, and transmits the eight parallel output data signals and the output clock signal.

Claim 14

The memory chip of claim 8, wherein; the receiver section comprises a receive control circuit coupled with the input port and the packet buffer, and a request queue coupled between the receive control circuit, the packet buffer and the memory array controller, and the transmitter section comprises a transmit control circuit coupled with the packet buffer, and a response queue coupled between the transmit control circuit, the packet buffer and the memory array controller.

Claim 15

The memory chip of claim 12, wherein; the receiver section further comprises a receive parity checker circuit coupled between the input port and the receive control circuit, and a row address comparator circuit coupled between the input port and the request queue, and the transmitter section further comprises a transmit parity generator circuit coupled between the packet buffer and the output port.

Claim 16

The memory chip of claim 12, wherein the request queue comprises an 8×5-bit static first-in-first-out memory array, and the response queue comprises an 8×4-bit static first-in-first-out memory array.

Claim 17

The memory chip of claim 8, wherein the packet buffer comprises a static random access memory array.

Claim 18

The memory chip of claim 8, wherein the packet buffer comprises an 8×146-bit static random access memory array and a 6×16-bit static first-in-first-out memory array.

Claim 19

The memory chip of claim 8, wherein the packet buffer comprises a 16×82-bit static random access memory array, an 8×64-bit static random access memory array and a 6×16-bit static first-in-first-out memory array.

Claim 20

The memory chip of claim 8, wherein the memory array comprises a dynamic random access memory array.

Claim 21

The memory chip of claim 8, wherein the memory array comprises a static random access memory array.

Claim 22

The memory chip of claim 8, wherein the memory array controller comprises a finite state machine which maximizes memory array access performance by arbitrating between memory array access commands and refresh requests based on memory array constraints.

Claim 23

The memory chip of claim 8, wherein the memory array and memory array controller include an error circuit that performs single-bit error detection and correction.

Claim 24

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates, comprising: a plurality of memory arrays, coupled with a memory array controller, that decode, arbitrate between, and execute memory array access commands, and generate memory array access responses; and a high bandwidth data interface, coupled with the plurality of memory arrays and the memory array controller, comprising; a unidirectional input port, a unidirectional output port, a packet buffer, and an interface controller that includes a receiver section, and a transmitter section, said unidirectional input port is coupled with the packet buffer and the receiver section, and receives an input data stream comprising memory array access commands, forwarding data and an input clock signal, said unidirectional output port is coupled with the packet buffer and the transmitter section, and transmits an output data stream comprising memory array access responses, forwarding data and an output clock signal, said receiver section, is coupled with the packet buffer and the memory array controller, and decodes and controls flow of the input data stream from the input port to the packet buffer, and to the plurality of memory arrays and the memory array controller, said transmitter section, is coupled with the packet buffer and the memory array controller, and controls flow of the output data stream from the packet buffer to the output port, and said packet buffer is coupled between the input and output ports and the plurality of memory arrays, and stores the memory array access commands prior to servicing by the plurality of memory arrays and the memory array controller, and stores the memory array access responses and the forwarding data prior to servicing by the transmitter section, and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller or plurality of memory arrays.

Claim 25

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates, comprising: a plurality of memory arrays, coupled with a memory array controller, that decode, arbitrate between, and execute memory array access commands, and generate memory array access responses; and a high bandwidth data interface, coupled with the plurality of memory arrays and the memory array controller, comprising; a unidirectional input port, a unidirectional output port, a packet buffer, and an interface controller that includes a receiver section, and a transmitter section, said unidirectional input port is coupled with the packet buffer and the receiver section, and receives an input data stream comprising memory array access commands, forwarding data and an input clock signal, said unidirectional output port is coupled with the packet buffer and the transmitter section, and transmits an output data stream comprising memory array access responses, forwarding data and an output clock signal, said receiver section, is coupled with the packet buffer and the memory array controller, and decodes and controls flow of the input data stream from the input port to the packet buffer, and to the plurality of memory arrays and the memory array controller, said transmitter section, is coupled with the packet buffer and the memory array controller, and controls flow of the output data stream from the packet buffer to the output port, and said packet buffer is coupled between the input and output ports and the plurality of memory arrays, and stores the memory array access commands prior to servicing by the plurality of memory arrays and the memory array controller, and stores the memory array access responses and the forwarding data prior to servicing by the transmitter section, and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller or plurality of memory arrays.

Claim 26

The memory chip of claim 22, wherein the input port comprises a plurality of input receivers configured in parallel, and the output port comprises a plurality of output drivers configured in parallel.

Claim 27

The memory chip of claim 23, wherein the input port further comprises a demultiplexer coupled with the plurality of input receivers, and the output port further comprises a multiplexer coupled with the plurality of output drivers.

Claim 28

The memory chip of claim 22, wherein; the input port comprises nine input receivers that receive an input clock signal having both rising and falling edges, and receive eight parallel input data signals with said parallel input data signals being clocked on both the rising and falling edges of the input clock signal, said nine input receivers are coupled with an eight-bit to sixteen-bit demultiplexer for converting the eight parallel input data signals to sixteen parallel input data signals clocked only on either the rising or the falling edges of the input clock signal, and the output port comprises a sixteen-bit to eight-bit multiplexer, clocked by an output clock signal having both rising and falling edges, that converts sixteen parallel output data signals clocked only on either the rising or the falling edges of the output clock signal to eight parallel output data signals clocked on both the rising and falling edges of the output clock signal, said sixteen-bit to eight-bit multiplexer is coupled with nine output drivers that transmit the eight parallel output data signals and the output clock signal.

Claim 29

The memory chip of claim 22, wherein; the receiver section comprises a receive control circuit coupled with the input port and the packet buffer, and a plurality of request queues coupled between the receive control circuit, the packet buffer and the memory array controller, and the transmitter section comprises a transmit control circuit coupled with the packet buffer, and a response queue coupled between the transmit control circuit, the packet buffer and the memory array controller.

Claim 30

The memory chip of claim 26, wherein; the receiver section further comprises a receive parity checker circuit coupled between the input port and the receive control circuit, and a row address comparator circuit coupled between the input port and the plurality of request queues, and the transmitter section further comprises a transmit parity generator circuit coupled between the packet buffer and the output port.

Claim 31

The memory chip of claim 26, wherein each of the plurality of request queues comprises an 8×5-bit static first-in-first-out memory array, and the response queue comprises an 8×4-bit static first-in-first-out memory array.

Claim 32

The memory chip of claim 22, wherein the packet buffer comprises a static random access memory array.

Claim 33

The memory chip of claim 22, wherein the packet buffer comprises an 8×145-bit static random access memory array and a 6×16-bit static first-in-first-out memory array.

Claim 34

The memory chip of claim 22, wherein the packet buffer comprises a 16×81-bit static random access memory array, an 8×64-bit static random access memory array and a 6×16-bit static first-in-first-out memory array.

Claim 35

The memory chip of claim 22, wherein the plurality of memory arrays comprise a plurality of dynamic random access memory arrays.

Claim 36

The memory chip of claim 22, wherein the plurality of memory arrays comprises a plurality of static random access memory arrays.

Claim 37

The memory chip of claim 22, wherein the memory array controller comprises a finite state machine which maximizes memory array access performance by arbitrating between memory array access commands and refresh requests based on memory array constraints.

Claim 38

The memory chip of claim 22, wherein the memory array and memory array controller include an error circuit that performs single-bit error detection and correction.

Claim 39

A high bandwidth data interface, comprising: a data path, an interface controller, a slave port and a packet buffer; said data path is coupled with the packet buffer and interface controller, and receives an input data stream through an input port and transmits an output data stream through an output port; said interface controller is coupled with the packet buffer, and controls flow of the input and output data streams within the high bandwidth data interface; and said packet buffer is coupled between the data path and the slave port, and temporarily stores data from the input and output data streams and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller.

Claim 40

A high bandwidth data interface, comprising: a data path, an interface controller, a slave port and a packet buffer; said data path is coupled with the packet buffer and interface controller, and receives an input data stream through an input port and transmits an output data stream through an output port; said interface controller is coupled with the packet buffer, and controls flow of the input and output data streams within the high bandwidth data interface; and said packet buffer is coupled between the data path and the slave port, and temporarily stores data from the input and output data streams and includes a data path through a forward queue that directly links the input port to the output port for forwarding data through the packet buffer without being processed by the interface controller.

Claim 41

The high bandwidth data interface of claim 36, wherein the input port comprises a plurality of input receivers configured in parallel, and the output port comprises a plurality of output drivers configured in parallel.

Claim 42

The high bandwidth data interface of claim 36, wherein; the input port comprises nine input receivers that receive an input clock signal having both rising and falling edges, and receive eight parallel input data signals with said parallel input data signals being clocked on both the rising and falling edges of the input clock signal, said nine input receivers are coupled with an eight-bit to sixteen-bit demultiplexer that converts the eight parallel input data signals to sixteen parallel input data signals clocked only on either the rising or the falling edges of the input clock signal, and the output port comprises a sixteen-bit to eight-bit multiplexer, clocked by an output clock signal having both rising and falling edges, and converts sixteen parallel output data signals clocked only on either the rising or the falling edges of the output clock signal to eight parallel output data signals clocked on both the rising and falling edges of the output clock signal, said sixteen-bit to eight-bit multiplexer is coupled with nine output drivers that transmit the eight parallel output data signals and the output clock signal.

Claim 43

The high bandwidth data interface of claim 36, wherein the interface controller comprises: a receiver section having a receive control circuit coupled with the data path and the packet buffer, and a request queue coupled between the receive control circuit and the packet buffer; and a transmitter section having a transmit control circuit coupled with the packet buffer, and a response queue coupled with the transmit control circuit and the packet buffer.

Claim 44

The high bandwidth data interface of claim 36, wherein the packet buffer comprises a static random access memory array.

Claim 47

The method for processing a stream of data of claim 41, wherein each input packet's plurality of fixed bit length data fields comprises a module address for addressing a particular device, a command field for specifying a request type, and a link identifier for linking a particular input packet with a particular output packet.

Claim 48

The method for processing a stream of data of claim 41, wherein each input packet and each output packet includes a checkbyte for error detection.

Claim 49

The method for processing a stream of data of claim 42, wherein the plurality of fixed bit length data fields of each input packet further comprises a request address.

Claim 50

The method for processing a stream of data of claim 44, wherein the plurality of fixed bit length data fields of each of certain input packets further comprises a write data word.

Claim 51

The method for processing a stream of data of claim 44, wherein the plurality of fixed bit length data fields of each of certain output packets further comprises a read data word.