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US5778028A
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DC removal circuit for digital signal
Assignee: LG Electronics Inc
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Filing: 1995-12-08
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Granted: 1998-07-07
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Expires: 2015-12-08
Abstract
Abstract A DC removal circuit for removing residual DC from a digitally encoded television signal including a plurality of multi level data symbols occurring at a constant symbol rate and formatted in repetitive data fields, each field including repetitive data segments having data segment sync of a fixed pattern of four symbols. A derived value of DC is subtracted from each of the received data symbols. The output of the subtractor is sampled, at the symbol rate or at one-half the symbol rate, and the sampled output is accumulated in an accumulator for generating the derived value. The sampling is continuous. The accumulator is preset to a zero value upon tuning to a different channel. An equalizer is supplied with the derived value of DC.
Inventors
- 👤 Rudolf Turner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:10
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/061; H04L25/063; H04L25/064
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
76 words
A method of removing DC from a digitally encoded input signal comprising a plurality of multi level data symbols received at a constant symbol rate comprising: subtracting a derived value from each of the data symbols for removing the DC component of each encoded input signal and producing a subtracted signal output; sampling said subtracted signal output at said symbol rate or at one-half said symbol rate; and accumulating the samples for generating said derived value.
Claim 2
Independent Claim
76 words
A method of removing DC from a digitally encoded input signal comprising a plurality of multi level data symbols received at a constant symbol rate comprising: subtracting a derived value from each of the data symbols for removing the DC component of each encoded input signal and producing a subtracted signal output; sampling said subtracted signal output at said symbol rate or at one-half said symbol rate; and accumulating the samples for generating said derived value.
Claim 3
Dependent Claim
32 words
The method of claim 1 wherein said encoded input signal is a television channel and further comprising restarting said accumulating step from a preset value upon tuning to a different television channel.
Claim 4
Dependent Claim
21 words
The method of claim 2 wherein said encoded input signal includes a DC pilot and wherein said preset value equals zero.
Claim 5
Dependent Claim
29 words
The method of claim 1 wherein said encoded input signal includes segment sync having a fixed pattern of four symbols and wherein said sampling also samples said segment sync.
Claim 6
Dependent Claim
14 words
The method of claim 1 wherein said sampling is continuous throughout said subtracted signal.
Claim 7
Dependent Claim
91 words
A DC removal circuit comprising: means for receiving a digitally encoded input signal comprising a plurality of multi level data symbols having a constant symbol rate and having levels above and below a zero value; subtracting means for subtracting a derived value from each of said multi level data symbols for substantially removing the DC component of said encoded input signal; means for sampling the output of said subtracting means at said symbol rate or at one-half said symbol rate; and means for accumulating the samples for generating said derived value.
Claim 8
Dependent Claim
91 words
A DC removal circuit comprising: means for receiving a digitally encoded input signal comprising a plurality of multi level data symbols having a constant symbol rate and having levels above and below a zero value; subtracting means for subtracting a derived value from each of said multi level data symbols for substantially removing the DC component of said encoded input signal; means for sampling the output of said subtracting means at said symbol rate or at one-half said symbol rate; and means for accumulating the samples for generating said derived value.
Claim 9
Dependent Claim
31 words
The circuit of claim 6 wherein said encoded input signal is a tuned television channel, and further including; means for resetting said accumulating means upon tuning to a different television channel.
Claim 10
Dependent Claim
18 words
The circuit of claim 7 wherein said resetting means presets said accumulating means to a value of zero.
Claim 11
Dependent Claim
30 words
The circuit of claim 6 wherein said encoded input signal includes segment sync having a fixed pattern of four symbols and wherein said sampling means also samples said segment sync.
Claim 12
Dependent Claim
18 words
The circuit of claim 6 wherein said sampling means operates continuously on said output of said subtracting means.
Claim 13
Independent Claim
62 words
A method of processing a digitally encoded input signal comprising a pilot and a plurality of multilevel data symbols received at a constant symbol rate, comprising: sampling said encoded signal at a rate equal to or less than the symbol rate; accumulating the samples for developing a DC signal representing said pilot; and using said DC signal to equalize said input signal.
Claim 14
Independent Claim
62 words
A method of processing a digitally encoded input signal comprising a pilot and a plurality of multilevel data symbols received at a constant symbol rate, comprising: sampling said encoded signal at a rate equal to or less than the symbol rate; accumulating the samples for developing a DC signal representing said pilot; and using said DC signal to equalize said input signal.
Claim 15
Dependent Claim
63 words
In combination: an equalizer; means for receiving a digitally encoded signal comprising a pilot and a plurality of constant rate multilevel data symbols; means for sampling said encoded signal at a rate equal to or less than the symbol rate; means for accumulating the samples for developing a DC signal representing said pilot; and means for applying said DC signal to said equalizer.
Claim 16
Dependent Claim
63 words
In combination: an equalizer; means for receiving a digitally encoded signal comprising a pilot and a plurality of constant rate multilevel data symbols; means for sampling said encoded signal at a rate equal to or less than the symbol rate; means for accumulating the samples for developing a DC signal representing said pilot; and means for applying said DC signal to said equalizer.
References Cited (Backward Citations)
US4071829A
Cited
US4878232A
Cited
US4985900A
Cited
US4972189A
Cited
US5416524A
Cited
US5475714A
Cited
US5565932A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |