Patent US5777512A successfully refreshed from Google Patents.
US5777512A
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Method and apparatus for oversampled, noise-shaping, mixed-signal processing
Assignee: Cirrus Logic Inc
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Filing: 1996-06-20
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Granted: 1998-07-07
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Expires: 2016-06-20
Abstract
Abstract A signal processing circuit is provided which includes a frequency selective network in a feedback loop for noise shaping purposes. A sampling analog-to-digital converter in the feedback loop operates at a sample frequency substantially above the Nyquist frequency. A switching device is driven by the sampling analog-to-digital converter and produces a continuous-time output signal which is continuously monitored by and fed back to the frequency selective network for noise and distortion correction in the feedback loop. This is in contrast to traditional techniques which employ only state feedback. State feedback (i.e., digital or sampled) of the output of the analog-to-digital converter may also be employed in combination with the continuous-time feedback of the switching device output.
Inventors
- 👤 Adya S. Tripathi
- 👤 Cary L. Delano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:47
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/38; H03F3/00; H03F3/20; H03F3/21; H03F3/217; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/324; H03M3/344; H03F2200/00; H03F2200/331; H03M3/358; H03M3/39; H03M3/412; H03M3/422; H03M3/43; H03M3/436; H03M3/438
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
123 words
An oversampled, noise-shaping, mixed-signal processor, comprising: at least one integrator stage in a feedback loop, the at least one integrator stage having an input; a discrete time sampling stage in the feedback loop coupled to the at least one integrator stage, the discrete time sampling stage for sampling an analog signal at a sample frequency only at discrete time intervals; a switching stage in the feedback loop coupled to the sampling stage, the switching stage having an input and an output; and a continuous-time feedback path from the output of the switching stage to the input of the at least one integrator stage thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to the sample frequency.
Claim 2
Dependent Claim
123 words
An oversampled, noise-shaping, mixed-signal processor, comprising: at least one integrator stage in a feedback loop, the at least one integrator stage having an input; a discrete time sampling stage in the feedback loop coupled to the at least one integrator stage, the discrete time sampling stage for sampling an analog signal at a sample frequency only at discrete time intervals; a switching stage in the feedback loop coupled to the sampling stage, the switching stage having an input and an output; and a continuous-time feedback path from the output of the switching stage to the input of the at least one integrator stage thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to the sample frequency.
Claim 3
Dependent Claim
42 words
The oversampled, noise-shaping, mixed-signal processor of claim 1 wherein the processor comprises a plurality of integrator stages, the processor further comprising a state feedback path from the input of the switching stage to at least one of the plurality of integrator stages.
Claim 4
Dependent Claim
45 words
The oversampled, noise-shaping, mixed-signal processor of claim 2 further comprising at least one adder coupled to the continuous-time feedback path and the state feedback path for providing a combination of continuous-time feedback and state feedback to at least one of the plurality of integrator stages.
Claim 5
Dependent Claim
21 words
The oversampled, noise-shaping, mixed-signal processor of claim 1 wherein the reducing means comprise an anti-aliasing filter in the continuous-time feedback path.
Claim 6
Dependent Claim
26 words
The oversampled, noise-shaping, mixed-signal processor of claim 1 wherein the processor comprises a plurality of integrator stages, at least one of which comprises a continuous-time integrator.
Claim 7
Dependent Claim
26 words
The oversampled, noise-shaping, mixed-signal processor of claim 1 wherein the processor comprises a plurality of integrator stages, at least one of which comprises a sampled integrator.
Claim 8
Dependent Claim
20 words
The oversampled, noise-shaping, mixed-signal processor of claim 6 wherein the sampled integrator is oversampled with respect to the sample frequency.
Claim 9
Dependent Claim
22 words
The oversampled, noise-shaping, mixed-signal processor of claim 1 further comprising means for introducing a dithering signal for the purpose of tone elimination.
Claim 10
Dependent Claim
134 words
A switching power amplifier, comprising: a first integrator stage in a feedback loop, the first integrator stage having an input; a second integrator stage in the feedback loop coupled to the first integrator stage, the second integrator stage having an input; a discrete time comparator stage in the feedback loop coupled to the second integrator stage; a power switching stage in the feedback loop, the power switching stage having an input and an output, the input of the power switching stage being coupled to the comparator stage; and a continuous-time feedback path from the output of the power switching stage to the input of at least one of the first and second integrator stages thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to a sample frequency.
Claim 11
Dependent Claim
134 words
A switching power amplifier, comprising: a first integrator stage in a feedback loop, the first integrator stage having an input; a second integrator stage in the feedback loop coupled to the first integrator stage, the second integrator stage having an input; a discrete time comparator stage in the feedback loop coupled to the second integrator stage; a power switching stage in the feedback loop, the power switching stage having an input and an output, the input of the power switching stage being coupled to the comparator stage; and a continuous-time feedback path from the output of the power switching stage to the input of at least one of the first and second integrator stages thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to a sample frequency.
Claim 12
Dependent Claim
35 words
The switching power amplifier of claim 9 further comprising a state feedback path from the input of the power switching stage to the input of at least one of the first and second integrator stages.
Claim 13
Dependent Claim
46 words
The switching power amplifier of claim 10 further comprising an adder coupled to the continuous-time feedback path, the state feedback path, and the input of at least one of the first and second integrator stages, the adder providing a combination of continuous-time and state feedback thereto.
Claim 14
Dependent Claim
20 words
The switching power amplifier of claim 9 wherein the reducing means comprise an anti-aliasing filter in the continuous-time feedback path.
Claim 15
Dependent Claim
18 words
The switching power amplifier of claim 9 wherein the power switching stage comprises a plurality of DMOS transistors.
Claim 16
Dependent Claim
19 words
The switching power amplifier of claim 13 wherein the plurality of DMOS amplifiers are arranged in an H-bridge configuration.
Claim 17
Dependent Claim
21 words
The switching power amplifier of claim 9 further comprising means for introducing a dithering signal for the purpose of tone elimination.
Claim 18
Dependent Claim
156 words
A switching power amplifier, comprising: a first integrator stage in a feedback loop, the first integrator stage having an input; a second integrator stage in the feedback loop coupled to the first integrator stage, the second integrator stage having an input; a third integrator stage in the feedback loop coupled to the second integrator stage, the third integrator stage having an input; a discrete time comparator stage in the feedback loop coupled to the third integrator stage; a power switching stage in the feedback loop, the power switching stage having an input and an output, the input of the power switching stage being coupled to the comparator stage; and a continuous-time feedback path from the output of the power switching stage to the input of at least one of the first, second and third integrator stages thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to a sample frequency.
Claim 19
Dependent Claim
156 words
A switching power amplifier, comprising: a first integrator stage in a feedback loop, the first integrator stage having an input; a second integrator stage in the feedback loop coupled to the first integrator stage, the second integrator stage having an input; a third integrator stage in the feedback loop coupled to the second integrator stage, the third integrator stage having an input; a discrete time comparator stage in the feedback loop coupled to the third integrator stage; a power switching stage in the feedback loop, the power switching stage having an input and an output, the input of the power switching stage being coupled to the comparator stage; and a continuous-time feedback path from the output of the power switching stage to the input of at least one of the first, second and third integrator stages thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to a sample frequency.
Claim 20
Dependent Claim
74 words
The switching power amplifier of claim 16 further comprising: an adder coupled to the continuous-time feedback path and to the input of at least one of the first, second and third integrator stages; a state feedback path from the input of the power switching stage to the adder; wherein the adder provides a combination of continuous-time and state feedback to the input of at least one of the first, second and third integrator stages.
Claim 21
Dependent Claim
20 words
The switching power amplifier of claim 16 wherein the reducing means comprises and anti-aliasing filter in the continuous-time feedback path.
Claim 22
Dependent Claim
18 words
The switching power amplifier of claim 16 wherein the power switching stage comprises a plurality of DMOS transistors.
Claim 23
Dependent Claim
19 words
The switching power amplifier of claim 19 wherein the plurality of DMOS amplifiers are arranged in an H-bridge configuration.
Claim 24
Dependent Claim
21 words
The switching power amplifier of claim 16 further comprising means for introducing a dithering signal for the purpose of tone elimination.
Claim 25
Dependent Claim
68 words
A signal processing method comprising the steps of: introducing an input signal to a frequency selective network thereby generating a frequency-selected signal; sampling the frequency-selected signal only at discrete time intervals at a predefined sample frequency, thereby generating a sampled signal; switching the sampled signal thereby generating a continuous-time output signal; and feeding back the continuous-time output signal to the frequency selective network thereby generating a noise-shaped signal.
Claim 26
Dependent Claim
68 words
A signal processing method comprising the steps of: introducing an input signal to a frequency selective network thereby generating a frequency-selected signal; sampling the frequency-selected signal only at discrete time intervals at a predefined sample frequency, thereby generating a sampled signal; switching the sampled signal thereby generating a continuous-time output signal; and feeding back the continuous-time output signal to the frequency selective network thereby generating a noise-shaped signal.
Claim 27
Dependent Claim
36 words
The method of claim 22 wherein the introducing step is performed by at least one integrator stage, the method further comprising the step of feeding back the sampled signal to the at least one integrator stage.
Claim 28
Dependent Claim
39 words
The method of claim 23 further comprising the steps of: combining the continuous-time output signal and the sampled signal thereby generating a combined feedback signal; and feeding back the combined feedback signal to the at least one integrator stage.
Claim 29
Dependent Claim
13 words
The method of claim 22 further comprising the step of reducing aliasing effects.
Claim 30
Dependent Claim
29 words
The method of claim 25 wherein the reducing step comprises filtering the continuous-time output signal with an anti-aliasing filter before the feeding it back to the frequency selective network.
Claim 31
Dependent Claim
33 words
The method of claim 25 wherein the frequency selective network comprises at least one sampled stage, the reducing step comprising oversampling the at least one sampled stage with respect to the sample frequency.
Claim 32
Dependent Claim
30 words
The method of claim 25 wherein the frequency selective network comprises at least one integrator stage, the reducing step comprising providing the at least one integrator stage with anti-aliasing characteristics.
Claim 33
Dependent Claim
24 words
The method of claim 22 further comprising the step of introducing a dithering signal to the frequency-selected signal for the purpose of tone elimination.
Claim 34
Dependent Claim
13 words
The method of claim 22 wherein the input signal comprises an analog signal.
Claim 35
Dependent Claim
13 words
The method of claim 22 wherein the input signal comprises a digital signal.
Claim 36
Dependent Claim
78 words
A signal processing circuit, comprising: a frequency selective network in a feedback loop; a sampling analog-to-digital converter in the feedback loop, the sampling analog-to-digital converter being sampled at a sample frequency; a switching device coupled to be driven by the sampling analog-to-digital converter to produce a continuous-time output signal; and means for continuously sensing and feeding back the continuous-time output signal to the frequency selective network for noise and distortion correction in the feedback loop and noise shaping.
Claim 37
Dependent Claim
78 words
A signal processing circuit, comprising: a frequency selective network in a feedback loop; a sampling analog-to-digital converter in the feedback loop, the sampling analog-to-digital converter being sampled at a sample frequency; a switching device coupled to be driven by the sampling analog-to-digital converter to produce a continuous-time output signal; and means for continuously sensing and feeding back the continuous-time output signal to the frequency selective network for noise and distortion correction in the feedback loop and noise shaping.
Claim 38
Dependent Claim
21 words
The signal processing circuit of claim 32 wherein the frequency selective network is an analog frequency selective network having anti-aliasing characteristics.
Claim 39
Dependent Claim
30 words
The signal processing circuit of claim 32 wherein the frequency selective network is an analog frequency selective network, and wherein the sensing and feeding back means comprises an anti-aliasing filter.
Claim 40
Dependent Claim
18 words
The signal processing circuit of claim 32 wherein the frequency selective network is a sampled frequency selective network.
Claim 41
Dependent Claim
21 words
The signal processing circuit of claim 35 wherein the sampled frequency selective network is oversampled with respect to the sample frequency.
Claim 42
Dependent Claim
18 words
The signal processing circuit of claim 35 wherein the sensing and feeding back means comprises an anti-aliasing filter.
Claim 43
Dependent Claim
18 words
The signal processing circuit of claim 32 wherein the frequency selective network comprises at least one integrator stage.
Claim 44
Dependent Claim
18 words
The signal processing circuit of claim 32 wherein the frequency selective network comprises at least one resonator stage.
Claim 45
Dependent Claim
16 words
The signal processing circuit of claim 32 wherein the sampling analog-to-digital converter comprises a two-level quantizer.
Claim 46
Dependent Claim
16 words
The signal processing circuit of claim 32 wherein the sampling analog-to-digital converter comprises an n-level quantizer.
Claim 47
Dependent Claim
20 words
The signal processing circuit of claim 32 wherein the frequency selective network is configured to receive an analog input signal.
Claim 48
Dependent Claim
20 words
The signal processing circuit of claim 32 wherein the frequency selective network is configured to receive a digital input signal.
Claim 49
Dependent Claim
148 words
An oversampled, noise-shaping, mixed-signal processor, comprising: at least one integrator stage in a feedback loop, the at least one integrator stage having an input; a sampling stage in the feedback loop coupled to the at least one integrator stage, the sampling stage for sampling an analog signal at a sample frequency; a switching stage in the feedback loop coupled to the sampling stage, the switching stage having an input and an output; and a continuous-time feedback path from the output of the switching stage to the input of the at least one integrator stage thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to the sample frequency, wherein the processor comprises a plurality of integrator stages, the processor further comprising a state feedback path from the input of the switching stage to at least one of the plurality of integrator stages.
Claim 50
Dependent Claim
148 words
An oversampled, noise-shaping, mixed-signal processor, comprising: at least one integrator stage in a feedback loop, the at least one integrator stage having an input; a sampling stage in the feedback loop coupled to the at least one integrator stage, the sampling stage for sampling an analog signal at a sample frequency; a switching stage in the feedback loop coupled to the sampling stage, the switching stage having an input and an output; and a continuous-time feedback path from the output of the switching stage to the input of the at least one integrator stage thereby closing the feedback loop, the feedback loop also including means for reducing aliasing effects corresponding to the sample frequency, wherein the processor comprises a plurality of integrator stages, the processor further comprising a state feedback path from the input of the switching stage to at least one of the plurality of integrator stages.
Claim 51
Dependent Claim
45 words
The oversampled, noise-shaping, mixed-signal processor of claim 44 further comprising at least one adder coupled to the continuous-time feedback path and the state feedback path for providing a combination of continuous-time feedback and state feedback to at least one of the plurality of integrator stages.
Claim 52
Dependent Claim
26 words
The oversampled, noise-shaping, mixed-signal processor of claim 44 wherein the processor comprises a plurality of integrator stages, at least one of which comprises a sampled integrator.
Claim 53
Dependent Claim
20 words
The oversampled, noise-shaping, mixed-signal processor of claim 46 wherein the sampled integrator is oversampled with respect to the sample frequency.
Claim 54
Dependent Claim
22 words
The oversampled, noise-shaping, mixed-signal processor of claim 44 further comprising means for introducing a dithering signal for the purpose of tone elimination.
Claim 55
Dependent Claim
96 words
A signal processing method comprising the steps of: introducing an input signal to a frequency selective network thereby generating a frequency-selected signal; sampling the frequency-selected signal at intervals at a sample frequency, thereby generating a sampled signal; switching the sampled signal thereby generating a continuous-time output signal; and feeding back the continuous-time output signal to the frequency selective network while reducing aliasing effects thereby generating a noise-shaped signal, wherein the frequency selective network comprises at least one sampled stage, the reducing step comprising oversampling the at least one sampled stage with respect to the sample frequency.
Claim 56
Dependent Claim
96 words
A signal processing method comprising the steps of: introducing an input signal to a frequency selective network thereby generating a frequency-selected signal; sampling the frequency-selected signal at intervals at a sample frequency, thereby generating a sampled signal; switching the sampled signal thereby generating a continuous-time output signal; and feeding back the continuous-time output signal to the frequency selective network while reducing aliasing effects thereby generating a noise-shaped signal, wherein the frequency selective network comprises at least one sampled stage, the reducing step comprising oversampling the at least one sampled stage with respect to the sample frequency.
Claim 57
Dependent Claim
78 words
A signal processing method comprising the steps of: introducing an input signal to a frequency selective network thereby generating a frequency-selected signal; sampling the frequency-selected signal at intervals at a sample frequency, thereby generating a sampled signal; switching the sampled signal thereby generating a continuous-time output signal; feeding back the continuous-time output signal to the frequency selective network thereby generating a noise-shaped signal; and introducing a dithering signal to the frequency-selected signal for the purpose of tone elimination.
Claim 58
Dependent Claim
78 words
A signal processing method comprising the steps of: introducing an input signal to a frequency selective network thereby generating a frequency-selected signal; sampling the frequency-selected signal at intervals at a sample frequency, thereby generating a sampled signal; switching the sampled signal thereby generating a continuous-time output signal; feeding back the continuous-time output signal to the frequency selective network thereby generating a noise-shaped signal; and introducing a dithering signal to the frequency-selected signal for the purpose of tone elimination.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |