US5777488A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit I/O node useable for configuration input at reset and normal output at other times
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-04-19
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Granted: 1998-07-07
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Expires: 2016-04-19
Abstract
Abstract The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a "reset time" or "reset interval"), and is also used to display output information during normal operation. The pin is coupled to a memory device, so as to store configuration information received during the reset interval. The pin is also coupled to an output driver controlled by a gate which combines output data with a signal indicating reset time, so as to put the output driver into a high impedance state during reset time when the input configuration data is being stored into the device and to drive the pin with the output value during non-reset times. Thus, a user of the IC may cause the memory to receive configuration information from the pin at power-up or during another reset time, while having the pin output normal data at times other than the reset interval.
Inventors
- 👤 Stephen F. Dryer
- 👤 Rong-Hui Hu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
103 words
Apparatus comprising: an on-chip circuit integrated onto a semiconductor wafer, said circuit comprising a node disposed for coupling to an external pin, said node coupled to a driving circuit, said driving circuit including a transistor coupled between said node and a reference voltage and a logic gate coupled to a control input for said transistor, said logic gate being coupled to receive said reset signal and to receive a data signal, wherein said driving circuit is coupled to a source of a reset signal, said node is coupled to a memory, and said memory is coupled to said source of a reset signal.
Claim 2
Dependent Claim
103 words
Apparatus comprising: an on-chip circuit integrated onto a semiconductor wafer, said circuit comprising a node disposed for coupling to an external pin, said node coupled to a driving circuit, said driving circuit including a transistor coupled between said node and a reference voltage and a logic gate coupled to a control input for said transistor, said logic gate being coupled to receive said reset signal and to receive a data signal, wherein said driving circuit is coupled to a source of a reset signal, said node is coupled to a memory, and said memory is coupled to said source of a reset signal.
Claim 3
Dependent Claim
72 words
Apparatus comprising: an on-chip circuit integrated onto a semiconductor wafer, said circuit including a node disposed for coupling to an external pin, and a comparator coupled to said node and to a reference voltage, said node coupled to a driving circuit, said driving circuit coupled to a source of a reset signal, an output of said comparator coupled to a memory, and said memory coupled to said source of a reset signal.
Claim 4
Dependent Claim
72 words
Apparatus comprising: an on-chip circuit integrated onto a semiconductor wafer, said circuit including a node disposed for coupling to an external pin, and a comparator coupled to said node and to a reference voltage, said node coupled to a driving circuit, said driving circuit coupled to a source of a reset signal, an output of said comparator coupled to a memory, and said memory coupled to said source of a reset signal.
Claim 5
Independent Claim
130 words
A method of operating an on-chip circuit, said on-chip circuit being integrated onto a semiconductor wafer and comprising a node disposed for coupling to an external pin, said method comprising the steps of: coupling said node to a memory during a reset interval of a reset signal; coupling said node to a driving circuit during times other than during said reset interval; and causing said reset interval of said reset signal in response to said reset condition of said on-chip circuit; wherein said step of coupling said node to a driving circuit comprises the steps of coupling said node to a reference voltage using a switch, and controlling said switch using a logic gate, said logic gate being coupled to receive said reset signal and to receive a data signal.
Claim 6
Independent Claim
130 words
A method of operating an on-chip circuit, said on-chip circuit being integrated onto a semiconductor wafer and comprising a node disposed for coupling to an external pin, said method comprising the steps of: coupling said node to a memory during a reset interval of a reset signal; coupling said node to a driving circuit during times other than during said reset interval; and causing said reset interval of said reset signal in response to said reset condition of said on-chip circuit; wherein said step of coupling said node to a driving circuit comprises the steps of coupling said node to a reference voltage using a switch, and controlling said switch using a logic gate, said logic gate being coupled to receive said reset signal and to receive a data signal.
Claim 7
Independent Claim
84 words
A method of operating an on-chip circuit, said on-chip circuit being integrated onto a semiconductor wafer and comprising a node disposed for coupling to an external pin, said method comprising the steps of: coupling said node to a memory during a reset interval of a reset signal; coupling said node to a driving circuit during times other than during said reset interval; and comparing an input signal from said node with a reference voltage before said step of coupling said node to a memory.
Claim 8
Independent Claim
84 words
A method of operating an on-chip circuit, said on-chip circuit being integrated onto a semiconductor wafer and comprising a node disposed for coupling to an external pin, said method comprising the steps of: coupling said node to a memory during a reset interval of a reset signal; coupling said node to a driving circuit during times other than during said reset interval; and comparing an input signal from said node with a reference voltage before said step of coupling said node to a memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |