US5594362A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gatable level-pulling circuit
Assignee: SEIKO COMMUNICATIONS SYSTEM Inc
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Filing: 1995-10-13
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Granted: 1997-01-14
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Expires: 2015-10-13
Abstract
Abstract Integrated circuit components automatically establish or disable a level-pulling condition relative to a given input IC pin as a function of detected signal activity at such IC pin, A logic signal responsive to signal activity at the IC pin drives the gate of a field effect transistor (FET) to dynamically establish or disable level-pulling function at the IC pin. Alternative embodiments include a flop-flop register and an OR gate driving the gate of the FET.
Inventors
- 👤 Jeffrey R. Owen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K17/00; H03K17/30; H03K17/302
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
67 words
A level-pulling device for an integrated circuit device pin, the level-pulling device comprising: a level-pulling element coupling said pin to a selected electrical potential, said level-pulling device including a gate receiving a mode-setting signal selecting one of enabling level-pulling and disabling level-pulling by said level-pulling element relative to said pin; and a mode-setting element producing said mode-setting signal as a function of signal activity at said pin.
Claim 2
Dependent Claim
67 words
A level-pulling device for an integrated circuit device pin, the level-pulling device comprising: a level-pulling element coupling said pin to a selected electrical potential, said level-pulling device including a gate receiving a mode-setting signal selecting one of enabling level-pulling and disabling level-pulling by said level-pulling element relative to said pin; and a mode-setting element producing said mode-setting signal as a function of signal activity at said pin.
Claim 3
Dependent Claim
22 words
A device according to claim 1 wherein said signal activity includes a logic signal state opposite that established by said level-pulling element.
Claim 4
Independent Claim
17 words
A device according to claim I wherein said mode-setting element comprises a register maintaining said mode-setting signal.
Claim 5
Dependent Claim
14 words
A device according to claim 1 wherein said mode-setting element comprises an OR gate.
Claim 6
Dependent Claim
22 words
A device according to claim 1 wherein said level-pulling element comprises a field effect transistor having a gate receiving said mode-setting signal.
Claim 7
Dependent Claim
105 words
An integrated circuit device selectively responsive to an external signal, said integrated circuit device comprising: an electrical signal conductor for coupling said external signal to signal processing circuitry of said integrated circuit; a level-pulling device coupling said signal conductor to a selected electrical potential, said level-pulling device dictating resistance between said signal conductor and said selected electrical potential, a first state of said level-pulling device establishing a level-pulling function relative to said signal conductor and a second state thereof disabling a level-pulling function relative to said signal conductor; and a mode-driving device responsive to electrical potential at said signal conductor to drive said level-pulling device.
Claim 8
Dependent Claim
105 words
An integrated circuit device selectively responsive to an external signal, said integrated circuit device comprising: an electrical signal conductor for coupling said external signal to signal processing circuitry of said integrated circuit; a level-pulling device coupling said signal conductor to a selected electrical potential, said level-pulling device dictating resistance between said signal conductor and said selected electrical potential, a first state of said level-pulling device establishing a level-pulling function relative to said signal conductor and a second state thereof disabling a level-pulling function relative to said signal conductor; and a mode-driving device responsive to electrical potential at said signal conductor to drive said level-pulling device.
Claim 9
Dependent Claim
48 words
A device according to claim 6 wherein said signal conductor comprises a first portion electrically coupled to an external pin of said integrated circuit device and a second portion comprising an input buffer logically coupling said first portion and said signal processing circuitry of said integrated circuit device.
Claim 10
Dependent Claim
15 words
A device according to claim 6 wherein said level-pulling device is a field effect transistor.
Claim 11
Dependent Claim
21 words
A device according to claim 6 wherein said mode-driving device is a latch for maintaining a selected state of said gate.
Claim 12
Dependent Claim
27 words
A device according to claim 6 wherein said mode-driving device is a logic gate driving said gate in duration corresponding to the condition of said signal conductor.
Claim 13
Dependent Claim
14 words
A device according to claim 10 wherein said mode-driving device comprises an OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |