US5051622A
Expired / Lapsed
US
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Power-on strap inputs
Assignee: Intel Corp
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Filing: 1990-10-30
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Granted: 1991-09-24
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Expires: 2010-10-30
Abstract
Abstract A technique for providing external mode select information to a chip capable of operating in different modes without adding pin overhead. One of the normal signal pins of the chip is used as an input pin for a brief period of time at power-on before the chip becomes fully operational. During this time, a mode select signal from outside is communicated onto the pin and latched into the chip, where it remains during subsequent normal operation of the chip.
Inventors
- 👤 Robert M. Pleva
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:09
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/22; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
90 words
In an integrated circuit device with internal circuitry having a portion responsive to a mode select signal at a control input, and a portion coupled to a signal pin, the improvement comprising: a latch having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; and means for providing a clock signal to said clock input of said latch during a power-on reset interval, said means being operative to maintain said latch in its latched state beyond the reset interval.
Claim 2
Dependent Claim
90 words
In an integrated circuit device with internal circuitry having a portion responsive to a mode select signal at a control input, and a portion coupled to a signal pin, the improvement comprising: a latch having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; and means for providing a clock signal to said clock input of said latch during a power-on reset interval, said means being operative to maintain said latch in its latched state beyond the reset interval.
Claim 3
Dependent Claim
27 words
The improvement of claim 1 wherein said clock signal includes a signal transition occurring approximately halfway through the reset interval and to which said latch is responsive.
Claim 4
Dependent Claim
162 words
In the combination of an integrated circuit device ("chip") and external circuitry, the chip having internal circuitry having a portion responsive to a mode select signal at a control input and a portion coupled to a signal pin, the improvement comprising: a latch, on the chip having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; means for providing a power-on reset signal during a reset interval; means, off the chip, for supplying a mode selection level to the signal pin; means, on the chip, for providing a clock signal to said clock input of said latch during said reset interval, said means being operative to maintain said latch in its latched state beyond said reset interval; and means for isolating during said reset interval the signal pin from signals normally communicated between the chip's internal circuitry and the external circuitry to allow said latch to store said mode select signal.
Claim 5
Dependent Claim
162 words
In the combination of an integrated circuit device ("chip") and external circuitry, the chip having internal circuitry having a portion responsive to a mode select signal at a control input and a portion coupled to a signal pin, the improvement comprising: a latch, on the chip having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; means for providing a power-on reset signal during a reset interval; means, off the chip, for supplying a mode selection level to the signal pin; means, on the chip, for providing a clock signal to said clock input of said latch during said reset interval, said means being operative to maintain said latch in its latched state beyond said reset interval; and means for isolating during said reset interval the signal pin from signals normally communicated between the chip's internal circuitry and the external circuitry to allow said latch to store said mode select signal.
Claim 6
Dependent Claim
27 words
The improvement of claim 2 wherein said clock signal includes a signal transition occurring approximately halfway through the reset interval and to which said latch is responsive.
Claim 7
Dependent Claim
107 words
An integrated circuit device with internal circuitry having a portion responsive to a mode select signal at a control input, and a portion coupled through a driver to an output signal pin, the improvement comprising: a latch having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; means for disabling the driver coupled to the signal pin during a power-on reset interval; and means for providing a clock signal to said clock input of said latch during said reset interval, said means being operative to maintain said latch in its latched state beyond the reset interval.
Claim 8
Dependent Claim
107 words
An integrated circuit device with internal circuitry having a portion responsive to a mode select signal at a control input, and a portion coupled through a driver to an output signal pin, the improvement comprising: a latch having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; means for disabling the driver coupled to the signal pin during a power-on reset interval; and means for providing a clock signal to said clock input of said latch during said reset interval, said means being operative to maintain said latch in its latched state beyond the reset interval.
Claim 9
Dependent Claim
27 words
The improvement of claim 5 wherein said clock signal includes a signal transition occurring approximately halfway through the reset interval and to which said latch is responsive.
Claim 10
Dependent Claim
93 words
In an integrated circuit device with internal circuitry having a portion responsive to a mode select signal at a control input, and a portion coupled through a receiver to a signal pin, the improvement comprising: a latch having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; and means for providing a clock signal to said clock input of said latch during a power-on reset interval, said means being operative to maintain said latch in its latched state beyond said reset interval.
Claim 11
Dependent Claim
93 words
In an integrated circuit device with internal circuitry having a portion responsive to a mode select signal at a control input, and a portion coupled through a receiver to a signal pin, the improvement comprising: a latch having a data input coupled to the signal pin, a data output coupled to the control input, and a clock input; and means for providing a clock signal to said clock input of said latch during a power-on reset interval, said means being operative to maintain said latch in its latched state beyond said reset interval.
Claim 12
Dependent Claim
27 words
The improvement of claim 7 wherein said clock signal includes a signal transition occurring approximately halfway through the reset interval and to which said latch is responsive.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-23 | 1995-03-25 | 1995-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-23 | 1999-03-25 | 1999-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-23 | 2003-03-25 | 2003-09-24 | $7700.00 | Window Closed / Lapsed |