US5777359A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor flash memory device and fabrication method of same
Assignee: SK Hynix Inc
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Filing: 1996-12-27
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Granted: 1998-07-07
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Expires: 2016-12-27
Abstract
Abstract A semiconductor flash memory device comprises a substrate, a plurality of buried bit lines, an insulation film, a floating gate, an inter-layer insulation film, and a control gate formed on the inter-layer insulation film. The fabrication method comprises forming the patterned first insulation films on the substrate, forming the gate insulation film on the substrate and between the patterned first insulation films, depositing a first poly-silicon layer on the gate insulation film and the patterned first insulation film, forming a floating gate by etching the first poly-silicon layer, forming a second insulation film on each of the floating gate and the substrate having the buried bit lines therein, and forming a control gate on the second insulation film. The flash memory device realizes high yield rate due to the simplified fabrication steps and facilitated fabrication.
Inventors
- 👤 Kyeong Man Ra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:25
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
136 words
A semiconductor flash memory device, comprising: a substrate; a plurality of buried bit lines each having first and second regions, the first region having a depth greater than the second region; an insulation layer on the substrate between the buried bit lines, the insulation layer having an indentation in a lower portion therein so that a first portion adjacent to the first region of the buried bit lines is thinner than a second portion adjacent to the second region of the buried bit lines; a floating gate on the insulation layer and asymmetrical to the left and right thereof; an inter-layer insulation layer on the floating gate and the substrate over the buried bit lines; and a control gate on the inter-layer insulation layer, a portion of the control gate being positioned below the floating gate.
Claim 2
Dependent Claim
136 words
A semiconductor flash memory device, comprising: a substrate; a plurality of buried bit lines each having first and second regions, the first region having a depth greater than the second region; an insulation layer on the substrate between the buried bit lines, the insulation layer having an indentation in a lower portion therein so that a first portion adjacent to the first region of the buried bit lines is thinner than a second portion adjacent to the second region of the buried bit lines; a floating gate on the insulation layer and asymmetrical to the left and right thereof; an inter-layer insulation layer on the floating gate and the substrate over the buried bit lines; and a control gate on the inter-layer insulation layer, a portion of the control gate being positioned below the floating gate.
Claim 3
Dependent Claim
36 words
The memory device according to claim 1, wherein the insulation layer between the first portion and the substrate and the second portion and the substrate includes a gate oxide layer and a first insulation layer respectively.
Claim 4
Dependent Claim
30 words
The memory device according to claim 2, wherein the first insulation layer is selected from the group consisting of an oxide film, a nitride film, and an undoped poly-silicon film.
Claim 5
Dependent Claim
21 words
The memory device according to claim 2, wherein the first insulation layer has a thickness ranging from 300 Åto 500 Å.
Claim 6
Dependent Claim
152 words
A semiconductor flash memory device, comprising: a substrate; a plurality of buried bit lines each having first and second regions, the first region having a depth greater than the second region; an insulation layer on the substrate between the buried bit lines, the insulation layer having an indentation in a lower portion therein so that a first portion of the insulation layer adjacent to the first region of the buried bit lines is thinner than a second portion adjacent to the second region of the buried bit lines; a floating gate on the insulation film and asymmetrical to the left and right thereof, the floating gate having a vertical length greater than a horizontal length; an inter-layer insulation layer on the floating gate and the substrate over the buried bit lines; and a control gate on the inter-layer insulation layer, a portion of the control gate being positioned below the floating gate.
Claim 7
Dependent Claim
152 words
A semiconductor flash memory device, comprising: a substrate; a plurality of buried bit lines each having first and second regions, the first region having a depth greater than the second region; an insulation layer on the substrate between the buried bit lines, the insulation layer having an indentation in a lower portion therein so that a first portion of the insulation layer adjacent to the first region of the buried bit lines is thinner than a second portion adjacent to the second region of the buried bit lines; a floating gate on the insulation film and asymmetrical to the left and right thereof, the floating gate having a vertical length greater than a horizontal length; an inter-layer insulation layer on the floating gate and the substrate over the buried bit lines; and a control gate on the inter-layer insulation layer, a portion of the control gate being positioned below the floating gate.
Claim 8
Dependent Claim
35 words
The memory device according to claim 5, wherein the insulation layer between the first portion and the substrate and the second portion and the substrate includes a gate oxide layer and a first insulation layer.
Claim 9
Dependent Claim
30 words
The memory device according to claim 6, wherein the first insulation layer is selected from the group consisting of an oxide film, a nitride film, and an undoped poly-silicon film.
Claim 10
Dependent Claim
21 words
The memory device according to claim 6, wherein the first insulation layer has a thickness ranging from 300 Åto 500 Å.
References Cited (Backward Citations)
US4671849A
Cited
US4814041A
Cited
US4698128A
Cited
US5303185A
Cited
US5146291A
Cited
US5323039A
Cited
US4902377A
Cited
US5326999A
Cited
US5502321A
Cited
US5592000A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |