EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells

Claim 2

A programmable non-volatile memory array formed on a semiconductor substrate comprising: first and second split gate transistors each including: (a) a first channel region integrally formed in said substrate; (b) a floating gate of an electrically conductive material having a bit line defining edge, and said floating gate insulatively disposed over said first channel region; (c) a source region integrally formed in said substrate and spaced apart from said first channel region; (d) a second channel region integrally formed in said substrate and interposed between said first channel region and said source region and (e) a drain region integrally formed in said substrate adjacent to said first channel region and being partially disposed under said floating gate; a bit line region, integrally formed in said substrate to be continuous with and join said drain regions of the first and second split gate transistors, said bit line region having opposed first and second sides arranged in a direction not parallel to a horizontal direction, and said opposed bit line sides are arranged not to have the same columnar alignment along a direction that is orthogonal to said horizontal direction; and wherein said drain regions of said first and second split gate transistors are respectively: (a) positioned at said first and second sides of said bit line region; and (b) separated from each other in a vertical direction so as not to have the same horizontal row alignment.

Claim 3

The memory array of claim 1 wherein: said first split gate transistor is associated with a first horizontally extending row of transistors; said second split gate transistor is associated with a second horizontally extending row of transistors; and said first row and said second row of transistors are adjacent and are formed on said substrate.

Claim 4

The memory array of claim 1 wherein said bit line region is formed before the formation of fully defined floating gates.

Claim 5

The memory array of claim 1 wherein said bit line region is self aligned to the material of said floating gates that is not disposed over said channel regions.

Claim 6

The memory array of claim 1 wherein said drain region is self aligned to a single strait line defining edge of said floating gate thereby minimizing the length of the periphery of said bit line region.

Claim 7

The memory array of claim 1 wherein said floating gates have substantially the same top surface area and perimeter length.

Claim 8

The memory array of claim 1 wherein said bit line region is formed so that the horizontal distance between said opposed first and second bit line sides is equal or shorter than the vertical distance between said separated drain regions.

Claim 9

The memory array of claim 1 wherein each transistor further includes an isolation region having at least a first and a second sides; wherein said first side of said isolation region is adjacent said bit line region and said second side of said isolation region adjacent said first and second channel regions; and wherein the vertical distance between said separated drain regions is defined by said first side of said isolation region.

Claim 10

The memory array of claim 1 wherein each of said first and second transistors further includes a second insulated gate that is insulatively disposed over said second channel region and said floating gate.

Claim 11

The memory array of claim 1 wherein each of said floating gates having a surface area not facing said substrate, and wherein substantially all of said surface area contains the same dose of a floating gate impurities independent of the distance of a given point of said surface area from said bit line region; and wherein said floating gates and said bit line sides are arranged in a vertical direction that is orthogonal to said horizontal direction.

Claim 12

An array of non-volatile programmable memory cells formed on a semiconductor substrate comprising: a first impurities bit line formed in said substrate having a left edge and an opposed right edge, said bit line extending in a vertical direction; first, second and third rows of split gate transistors each formed on said substrate, each including a floating gate of an electrically conductive material and each row of said transistors connected by a connecting means that is extending in a horizontal direction to cross over said first impurities bit line; each of said floating gates having a surface area not facing said substrate and wherein substantially all of said surface area contains the same dose of a floating gate impurities independent of the distance of a given point of said surface area from said bit line; each said second row is interposed between said one first row and one third row; said second rows having their floating gates aligned along first vertical columns and said first and third rows having their floating gates aligned along second vertical columns, and said first floating gate columns are not in columnar alignment with said second floating gates columns; and wherein a first floating gate of the first row, overlaps a first right edge region of said first impurities bit line and a second floating gate of the second row, overlaps a first left edge region of said first impurities bit line.

Claim 13

An array of non-volatile programmable memory cells formed on a semiconductor substrate comprising: a first impurities bit line formed in said substrate having a left edge and an opposed right edge, said bit line extending in a vertical direction; first, second and third rows of split gate transistors each formed on said substrate, each including a floating gate of an electrically conductive material and each row of said transistors connected by a connecting means that is extending in a horizontal direction to cross over said first impurities bit line; each of said floating gates having a surface area not facing said substrate and wherein substantially all of said surface area contains the same dose of a floating gate impurities independent of the distance of a given point of said surface area from said bit line; each said second row is interposed between said one first row and one third row; said second rows having their floating gates aligned along first vertical columns and said first and third rows having their floating gates aligned along second vertical columns, and said first floating gate columns are not in columnar alignment with said second floating gates columns; and wherein a first floating gate of the first row, overlaps a first right edge region of said first impurities bit line and a second floating gate of the second row, overlaps a first left edge region of said first impurities bit line.

Claim 14

The memory array of claim 11 wherein each said split gate transistor further includes a control gate that is insulatively disposed over said floating gate and the structural geometrical width of a given control gate is smaller than the structural geometrical length of its associated floating ate.

Claim 15

A programmable non-volatile memory cell including a first and a second impurities regions formed along the surface of a semiconductor substrate comprising: a first polysilicon control electrode insulatively disposed over said substrate; a region of said substrate disposed between said first and said second impurities regions forming a channel region underlying said control electrode; said channel region consisting of a drain area disposed adjacent to said first impurities regions and a source area disposed adjacent to said second impurities region; said first impurities region, channel region, first control electrode, and second impurities region respectively forming the drain terminal, channel, control gate terminal, and source terminal of a field effect transistor that has a threshold voltage; a programmable floating gate electrode insulatively disposed over said drain area and under said control electrode and having a first coupling edge disposed alongside said first impurities region; a second control gate insulatively disposed along at least one side of said floating gate; and said first impurities region and said second control gate operable to capacitively couple said floating gate to said channel region so that said drain area is inverted but said source area is not inverted when said first impurities region is charged to a voltage that causes said floating gate to collect electrons for increasing the magnitude of the threshold voltage of said field effect transistor.

Claim 16

A programmable non-volatile memory cell including a first and a second impurities regions formed along the surface of a semiconductor substrate comprising: a first polysilicon control electrode insulatively disposed over said substrate; a region of said substrate disposed between said first and said second impurities regions forming a channel region underlying said control electrode; said channel region consisting of a drain area disposed adjacent to said first impurities regions and a source area disposed adjacent to said second impurities region; said first impurities region, channel region, first control electrode, and second impurities region respectively forming the drain terminal, channel, control gate terminal, and source terminal of a field effect transistor that has a threshold voltage; a programmable floating gate electrode insulatively disposed over said drain area and under said control electrode and having a first coupling edge disposed alongside said first impurities region; a second control gate insulatively disposed along at least one side of said floating gate; and said first impurities region and said second control gate operable to capacitively couple said floating gate to said channel region so that said drain area is inverted but said source area is not inverted when said first impurities region is charged to a voltage that causes said floating gate to collect electrons for increasing the magnitude of the threshold voltage of said field effect transistor.

Claim 17

The invention of claim 13 where said floating gate collects electrons from a terminal of said field effect transistor when said non-volatile memory cell is adapted to increase the magnitude of its threshold voltage.

Claim 18

The invention of claim 13 where said floating voltage collects electrons from said first control electrode of said filed effect transistor when said non-volatile memory cell is adapted to increase the magnitude of its threshold voltage.

Claim 21

The apparatus of claim 16 wherein said semiconductor substrate is of a first conductivity type; each of said channel regions is defined in said substrate between an associated drain region of a second conductivity type and an associated source region of a second conductivity type integrally formed in said substrate; and wherein one of said second conductivity type regions extends deeper into said substrate than the other second conductivity type region.

Claim 22

The apparatus of claim 16 wherein said semiconductor substrate is of a first conductivity type; each of said channel regions is defined in said substrate between an associated drain region of a second conductivity type and an associated source region of a second conductivity type integrally formed in said substrate; and wherein one of said second conductivity type regions includes higher impurities concentrations than the other second conductivity type region.

Claim 23

The apparatus of claim 16 further including: spacers of an insulating material having a dielectric constant; and said spacers are disposed alongside said elongated conductive strips and disposed over said impurities regions.

Claim 24

The apparatus of claim 16 wherein said impurities regions are partially disposed under only one side of said associated elongated conductive strip.

Claim 25

A programmable non-volatile memory, formed on a semiconductor substrate having a major surface, said memory comprising: an array of M×N programmable non-volatile memory cells organized into M rows oriented horizontally and N columns oriented vertically; said M rows are arranged into half of M pairs of adjacent two rows; at least one of said rows includes only a single charge emitting means that is common to plurality of memory cells within said given row, and not common to memory cells that are within a given column or are within adjacent rows; said charge emitting means is the only conductor means that is connected to plurality of memory cells within said given row of said array and is not connected to adjacent rows; and wherein each of said pairs of rows includes a common control line coupled to at least one memory cell within each row of said pair of rows.

Claim 26

A programmable non-volatile memory, formed on a semiconductor substrate having a major surface, said memory comprising: an array of M×N programmable non-volatile memory cells organized into M rows oriented horizontally and N columns oriented vertically; said M rows are arranged into half of M pairs of adjacent two rows; at least one of said rows includes only a single charge emitting means that is common to plurality of memory cells within said given row, and not common to memory cells that are within a given column or are within adjacent rows; said charge emitting means is the only conductor means that is connected to plurality of memory cells within said given row of said array and is not connected to adjacent rows; and wherein each of said pairs of rows includes a common control line coupled to at least one memory cell within each row of said pair of rows.

Claim 27

The memory device of claim 21 wherein each of said horizontal rows includes impurities regions that are integrally formed in said substrate, said impurities regions are positioned so that they are laterally spaced apart within each of said horizontal rows.

Claim 28

The memory of claim 21 wherein all horizontal rows of said array include the same number of said memory cell.

Claim 29

The memory of claim 21 wherein all horizontal rows of said array include an identical single charge emitting means.

Claim 30

The memory of claim 21 wherein said single charge emitting means is electrically insulated from said substrate.

Claim 31

The memory of claim 21 wherein each memory cell includes a floating gate and wherein said single charge emitting means is insulatively disposed over a row of said floating gates in at least one of said M horizontal rows.

Claim 32

The memory of claim 22 wherein said charge emitting means emits charge during programming of memory cells associated with its row.

Claim 33

The memory of claim 27 wherein each of said memory cells further includes an insulated floating gate and wherein said charge is absorbed by at least one of said floating gates that is associated with the corresponding horizontal row of said charge emitting means.

Claim 34

The memory of claim 28 wherein every two of said impurities regions form source and drain respectively of an electrically programmable MOS field effect transistor.