Method to test the running of a program of instructions carried out by an ASIC and ASIC pertaining thereto

Claim 3

A method according to claim 1, wherein the word to be stored is stored at the time of the performance of the instruction that the address is representative of.

Claim 4

A method according to one of the claim 1, wherein the stored address is the address of the first word of the instruction.

Claim 5

A method according to claim 1, wherein to store an address: the address is stored in the latch circuits when it is present on the address bus, the address is stored in the stack input register when it is decoded, and the address is stored in the stack when the instruction that the address is representative of is carried out.

Claim 6

A method according to claim 1, wherein the inputs of the first register of the stack are connected selectively by means of a multiplexer to the outputs of the stack input register or to the outputs of the last register of the stack.

Claim 7

A method according to claim 1, wherein the reading of the contents of the stack is done from the outputs of one of the registers of the stack, the inputs of the first register being connected to the outputs of the last register of the stack, the contents of the registers being successively transferred from one register to the next register.

Claim 8

A method according to claim 6, wherein the reading of the contents of the stack is done from the outputs of the first register of the stack.

Claim 9

A method according to claim 6 wherein, during the reading of the stack, the outputs of the register used for the reading are connected to a bus accessible from the exterior of the integrated circuit.

Claim 10

A method according to claim 8, wherein the bus used to read the contents of the stack is an n-bit data bus.

Claim 11

A method according to claim 1, wherein the application specific integrated circuit has means for storing, in a particular mode, in a shift register formed by elementary cells, each mounted on the lines of the application specific integrated circuit, the state of these lines when the performance of an instruction prompts a particular event.

Claim 12

A method according to claim 10, wherein the contents of the register of the stack corresponding to the address representative of the instruction that has prompted the event are stored in elementary cells of this shift register.

Claim 13

A method according to claim 11, wherein the elementary cells in which there are stored the contents of the register containing the address representative of the instruction that has prompted the event are connected to the lines of the instruction address bus when the particular mode is not selected.

Claim 14

A method according to claim 11, wherein the contents of the second register of the stack are stored in the shift register if the instruction following the one that has prompted the particular event is a multicycle event, and wherein the contents of the third register of the stack are stored in the shift register if the instruction following the one that has prompted the event is a one-cycle instruction.

Claim 15

A method according to claim 1, wherein the stack contains six registers.

Claim 16

An applications specific integrated circuit, comprising: a central processing unit; and devices dependent on the application of the application specific circuit; wherein these devices include at least one program memory; wherein the program memory includes a program of instructions to be carried out, each instruction having one or more words and lasting one or more cycles, and each word being stored at an address location in the program memory; wherein the application specific circuit further comprises address positioning circuits for positioning, by using a program counter, the address of the word or of the successive addresses of the words of the instruction on an n-bit instruction address bus, n being an integer, connecting the central processing unit to the program memory; data positioning circuits for positioning, by using the program memory, after the reading of each word, this word on an instruction data bus connecting the central processing unit to the memory; decoding circuits for decoding the words by a sequencer of the central processing unit; execution circuits for carrying out the instruction by the central processing unit; and storage means arranged for storing, during the processing of each instruction, the address of a word of this instruction and may be read during the processing of this instruction; wherein said storage means comprises p parallel-parallel registers with n inputs and n outputs, with p as an integer, series connected so as to form a stack and connected to the address bus by means of n latch circuits and one parallel-parallel stack input register with n inputs and n outputs; and wherein at least one instruction lasts more than one cycle.

Claim 17

An applications specific integrated circuit, comprising: a central processing unit; and devices dependent on the application of the application specific circuit; wherein these devices include at least one program memory; wherein the program memory includes a program of instructions to be carried out, each instruction having one or more words and lasting one or more cycles, and each word being stored at an address location in the program memory; wherein the application specific circuit further comprises address positioning circuits for positioning, by using a program counter, the address of the word or of the successive addresses of the words of the instruction on an n-bit instruction address bus, n being an integer, connecting the central processing unit to the program memory; data positioning circuits for positioning, by using the program memory, after the reading of each word, this word on an instruction data bus connecting the central processing unit to the memory; decoding circuits for decoding the words by a sequencer of the central processing unit; execution circuits for carrying out the instruction by the central processing unit; and storage means arranged for storing, during the processing of each instruction, the address of a word of this instruction and may be read during the processing of this instruction; wherein said storage means comprises p parallel-parallel registers with n inputs and n outputs, with p as an integer, series connected so as to form a stack and connected to the address bus by means of n latch circuits and one parallel-parallel stack input register with n inputs and n outputs; and wherein at least one instruction lasts more than one cycle.

Claim 18

The application specific circuit according to claim 15, wherein the storage means are arranged so that the address of the word is stored at the time of the performance of the instruction that the address is representative of.

Claim 19

The application specific circuit according to claims 15, wherein the storage means are arranged in such a way that, for each instruction, the stored address is the address of the first word of the instruction.

Claim 20

The application specific circuit according to claim 15, wherein the inputs of the first register of the stack are connected selectively by means of a multiplexer to the outputs of the stack input register or to the outputs of the last register of the stack.

Claim 21

The application specific circuit according to claim 15, comprising means to connect the outputs of a register of the stack to a bus accessible from the exterior of the integrated circuit.

Claim 22

The application specific circuit according to claim 15, comprising a shift register and means for the memorizing, in a particular mode, in this shift register formed by elementary cells mounted on lines of the integrated circuit, of the state of these lines when the performance of an instruction prompts a particular event.

Claim 23

The application specific circuit according to claim 20, comprising means to connect the outputs of the register of the stack, whose contents correspond to the address representative of the instruction that has prompted the event, to elementary cells of this shift register.

Claim 24

The application specific circuit according to claim 15, wherein the stack contains six registers.