EP0516172A2
Expired / Lapsed
EP
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Microprocessor with halt instruction
Assignee: NEC Corp
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Filing: 1992-05-29
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Granted: —
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Expires: 2012-05-29
Abstract
Abstract A microprocessor comprises a program counter (111, 112, 113) for holding the address where the halt instruction is detected, a terminal (123, 124, 125) for outputting a special status signal, a bus cycle control unit (105) for generating the halt instruction indication bus cycle, and an execution unit (103) for transferring the content of the program counter to the bus cycle control unit and requesting the start of the halt instruction indication bus cycle. Thus, the address where the processor halt instruction has been executed and other internal information are informed to an external, so that precise and certain debugging environment is obtained.
Inventors
- 👤 Hiroaki C/O Nec Corporation Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:59
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30079; G06F11/00; G06F11/30; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648; G06F9/38; G06F9/3867
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
89 words
A microprocessor which includes a particular instruction for executing an interrupt or a temporary halt of an instruction execution, comprising means for detecting said particular instruction and generating a bus cycle, first output means for outputting a particular status signal in synchronism with said generated bus cycle, and second output means for outputting the content of a program counter to one of an address bus and a data bus, so that the content of the program counter is informed to an external by the execution of said particular instruction.
Claim 2
Dependent Claim
80 words
A microprocessor claimed in Claim 1 wherein said second output means outputs the content of said program counter to said address bus, and further comprising third output means for outputting the content of a processor status word to said data bus in synchronism with the data bus cycle generated by the data cycle generating means, so that the contents of the program counter and the processor status word are informed to the external by the execution of said particular instruction.
Claim 3
Dependent Claim
280 words
A microprocessor which includes a particular instruction for executing an interrupt or a temporary halt of an instruction execution, comprising: a bus cycle controlling unit coupled to an external address bus and an external data bus; an instruction fetch unit coupled to said bus cycle controlling unit for controlling the start of a fetch cycle and for accumulating instruction codes fetched from an external in said fetch cycle; an instruction decoding unit coupled to said instruction fetch unit for decoding instruction codes accumulated in the instruction fetch unit and for generating signals indicative of a processing inherent to the respective instructions; an instruction executing unit controlled by said instruction decoding unit so as to execute a processing designated by said instruction decoding unit; an effective address calculation unit coupled to said instruction decoding unit and said instruction executing unit for calculating an address for an operand when said instruction decoding unit detects an instruction containing an access to a memory or an I/O device; a program counter for holding the address of instructions processed by said instruction executing unit, the microprocessor being controlled in such a manner that said decoding unit decodes said particular instruction, said decoding unit instructs said instruction fetch unit to stop the supply of succeeding instruction codes, and at the same time, the execution processing of said particular instruction is instructed to said instruction executing unit so that said instruction executing unit transfers a content of said program counter which then holds an address storing said particular instruction, to said bus cycle controlling unit, which in turn outputs said content of said program counter to one of said external address bus and said external data bus
References Cited (Backward Citations)
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