Method and apparatus for generating instruction/data streams employed to verify hardware implementations of integrated circuit designs

Claim 3

The method of claim 1, wherein the plurality of events of the instruction/data stream operate sequentially without intermediate reinitialization of the plurality of registers.

Claim 4

The method of claim 1: further comprising the step of receiving system element behavior, wherein system element behavior describes operation of system elements within the integrated circuit design; and wherein the step of processing the plurality of templates, the plurality of register models, and the plurality of exception events further includes processing the system element behavior.

Claim 5

The method of claim 3, wherein the system element behavior describes operations of system elements selected from the group consisting of at least memory management units, load/store units, cache memory units, receiver units, transmitter units, receiver/transmitter units, integer units, floating point units, coprocessors, arithmetic logic units, and input/output controllers.

Claim 6

The method of claim 1, wherein the plurality of register models includes a plurality of system register models and a plurality of general register models.

Claim 7

The method of claim 1, wherein the plurality of exception events includes a plurality of instruction based exception events and a plurality of hardware event based exception events.

Claim 8

The method of claim 1, wherein at least a plurality of the templates further include respective boundary conditions.

Claim 9

The method of claim 1, wherein the respective boundary conditions include operand values and pipeline sequences.

Claim 10

The method of claim 1, wherein the hardware implementation is selected from the group consisting of behavioral-level models, register-transfer-level models, resistor-transistor-level models, physical design file models, and silicon representations.

Claim 11

The method of claim 1, wherein processing includes, based upon user input: generating a sequence of instructions to initialize the hardware implementation to an initialized state; creating at least one instruction thread that verifies an operation of the hardware implementation for a respective template operating under a respective boundary condition; and creating at least one instruction thread that verifies contents of registers within the hardware implementation to verify the operation of the hardware implementation.

Claim 12

The method of claim 10, further comprising the step of creating instructions that cause the hardware implementation to compare actual resultants generated by the hardware implementation with expected resultants.

Claim 15

The method of claim 12, further comprising the steps of: receiving system element behavior, wherein system element behavior describes operation of system elements within the integrated circuit design; and generating a plurality of instruction threads based on the system element behavior that, when executed, verify a portion of an operation of the hardware implementation for a respective system element.

Claim 16

The method of claim 13, wherein the system element behavior describes operations of system elements selected from the group consisting of at least memory management units, load/store units, cache memory units, receiver units, transmitter units, receiver/transmitter units, integer units, floating point units, coprocessors, arithmetic logic units, and input/output controllers.

Claim 17

The method of claim 12, wherein the hardware implementation is selected from the group consisting of behavioral-level models, register-transfer-level models, resistor-transistor-level models, physical design file models, and silicon representations.

Claim 18

The method of claim 12, wherein the plurality of register models includes a plurality of system register models and a plurality of general register models.

Claim 19

The method of claim 12, wherein the plurality of exception events includes a plurality of instruction based exception events and a plurality of hardware event based exception events.

Claim 20

The method of claim 12, wherein the respective boundary conditions include operand values and pipeline sequences.

Claim 23

A computer readable storage device adapted for use with a digital computer such that the digital computer may read the computer readable storage device, wherein the computer readable storage device comprises: (a) a first plurality of storage locations, wherein the first plurality of storage locations store instructions for causing the digital computer to receive a plurality of templates, wherein each of the plurality of templates describes at least a partial behavior of the integrated circuit design for a respective instruction; (b) a second plurality of storage locations, wherein the second plurality of storage locations store instructions for causing the digital computer to receive a plurality of register models, wherein the plurality of register models describe the operation of a plurality of registers within the integrated circuit design; (c) a third plurality of storage locations, wherein the third plurality of storage locations store instructions for causing the digital computer to receive a plurality of exception events, wherein each of the plurality of exception events corresponds to a potentially problematic operation of the hardware implementation of the integrated circuit design; (d) a fourth plurality of storage locations, wherein the fourth plurality of storage locations store instructions for causing the digital computer to process the plurality of templates, the plurality of register models, and the plurality of exception events to produce the instruction/data stream, wherein the instruction/data stream includes a plurality of events, and wherein an execution of the instruction/data stream by the hardware implementation verifies the operation of the hardware implementation.

Claim 24

A computer readable storage device adapted for use with a digital computer such that the digital computer may read the computer readable storage device, wherein the computer readable storage device comprises: (a) a first plurality of storage locations, wherein the first plurality of storage locations store instructions for causing the digital computer to receive a plurality of templates, wherein each of the plurality of templates describes at least a partial behavior of the integrated circuit design for a respective instruction; (b) a second plurality of storage locations, wherein the second plurality of storage locations store instructions for causing the digital computer to receive a plurality of register models, wherein the plurality of register models describe the operation of a plurality of registers within the integrated circuit design; (c) a third plurality of storage locations, wherein the third plurality of storage locations store instructions for causing the digital computer to receive a plurality of exception events, wherein each of the plurality of exception events corresponds to a potentially problematic operation of the hardware implementation of the integrated circuit design; (d) a fourth plurality of storage locations, wherein the fourth plurality of storage locations store instructions for causing the digital computer to process the plurality of templates, the plurality of register models, and the plurality of exception events to produce the instruction/data stream, wherein the instruction/data stream includes a plurality of events, and wherein an execution of the instruction/data stream by the hardware implementation verifies the operation of the hardware implementation.