Application generator for use in verifying a hierarchical circuit design

Claim 2

A computer-implemented method for design verification of a physical design of a very large scale integrated (VLSI) circuit expressed in the form of hierarchical circuit design data, said method for design verification checking the hierarchical circuit design data in its most nested form and comprising the steps of: receiving a set of directives to be performed on the hierarchical circuit design data, said directives embodying design rule definitions for use in verifying compliance with design rules of the circuit design; performing a functional decomposition of the directives into primitive functions to perform the directives; establishing a primary iteration level for each directive; determining a data flow dependency for the directives; organizing the primitive functions based on the data flow dependency; generating an application program representative of the primitive functions by grouping together in clusters design rule checks and mask analysis operations that use a same base shape level, and establishing within each cluster a set of lists of shape instances (LISAs) required to perform design checks, the LISAs representing VLSI design component instances necessary to perform a set of directives on the hierarchical circuit accessing the hierarchical circuit design data; detecting intrusions between shape instances in the accessed hierarchical circuit design data; based on intrusions detected, processing LISAs for each checking cluster and dispatching checking functions; and outputting results of the checking functions indicating errors in the physical design of the VLSI circuit.

Claim 3

A computer-implemented method as recited in claim 1, further comprising the steps of: generating a humungous LISA by (a) invoking predetermined intrusion searches corresponding to a set of design rules, the intrusion searches producing pairs of instances of intruding VLSI design components; (b) sorting the search results by a preorder sequence number of an inverse placement graph representing the hierarchical circuit design; traversing the humungous LISA to extract the intrusion pairs which are elements of each of its constituent LISAs; and executing the directives requiting the data in each LISA in postorder sequence.

Claim 4

A computer-implemented method as recited in claim 2, wherein the step of traversing includes the steps of: defining a transform path spine for each LISA, the transform path spine including the state of the LISA traversal and the intruding shapes detected during the LISA traversal; and sequentially accessing the search results, and for each pair of sorted search results, (a) determining the postorder number of the VLSI design component instance of the base design component in the intruding pair, (b) determining which LISAs the intrusion pair will update, (c) for each LISA, comparing the postorder number of the intruding pair with the current postorder state of the LISA and (1) if pushing the data of the intruding pair onto the transform path spine of a LISA will cause the postorder state of the LISA to become smaller or remain the same, pushing the data onto the transform path spine stack of the LISA and updating the postorder state of the LISA, (2) if pushing the intruding pair onto the transform path spine of a LISA will cause the postorder state of the LISA to increase, causing the directives dependent on the LISA to be executed at the current state of the LISA and updating the instance counts of the sate, (3) popping from the stack the data stored at the just-executed postorder state and updating the state of the LISA, (d) upon completion of processing the sorted search results, processing the removing the remaining intrusion pairs in the LISA transform path spine stack.

Claim 5

A computer-implemented method as recited in claim 1, wherein the step of performing a functional decomposition further comprises the sub-step of: determining, for each primitive function, inputs to the function and properties associated with the primitive function, the properties including any requiring a LISA, requiring ancillary LISAs, and having dependent functions.

Claim 6

A computer-implemented method as recited in claim 4, wherein inputs to the function include derived shapes of the physical design.

Claim 7

A computer-implemented method as recited in claim 1, further comprising a step of optimizing the primitive functions prior to generating said application program by categorizing as expensive those primitive functions whose execution requires more than a predetermined threshold of computer resource; and allocating storage for caching results of the expensive primitive functions.

Claim 8

A computer-implemented method as recited in claim 1, further comprising a step of optimizing the primitive functions prior to generating said application program by sorting the directives into data-flow dependent clusters having common sets of primary iteration levels.

Claim 9

A computer-implemented method as recited in claim 7, further comprising the step of: determining for each cluster a set of LISAs required by the directives in the cluster, each LISA including a base level, an intruding level, a region of interest, anti a LISA type.

Claim 10

A computer-implemented method as recited in claim 8, further comprising the step of: determining n minimum number of intrusion searches from the base level, intruding level, and region of interest information stored in the LISAs.

Claim 11

A computer-implemented method as recited in claim 1, further comprising the step of generating in memory a template for each cluster, each template including a transform path spine for the cluster represented by the template, a transform path spine for each LISA in the cluster, and a transform path spine for each directive required by the cluster.

Claim 12

A computer-implemented method as recited in claim 10, wherein the template further includes space for caching of intermediate results generated during processing of LISAs, and pointers to directives associated with LISAs.

Claim 13

A computer-implemented method as recited in claim 10, further comprising the step of generating in memory an execution procedure for each directive, each execution procedure including programming code to determine if the directive has executed previously using the same inputs, and programming code to perform the directive.

Claim 14

A computer-implemented method as recited in claim 1, further comprising the steps of: generating LISAs by (a) invoking predetermined intrusion searches corresponding to a set of design rules, the intrusion searches producing pairs of instances of intruding VLSI design components; (b) storing the search results in a search graph; traversing the search graph in postorder sequence to extract the intruding VLSI design components and execute the directives dependent on the LISAs.

Claim 15

A computer system for verifying a physical design of a very large scale integrated (VLSI) circuit expressed in the form of hierarchical circuit design data, comprising: storage means for storing the hierarchical circuit design data; input means for receiving, a set of directives to be performed on the hierarchical circuit design data, the input directives embodying design rule definitions for use in verifying compliance with design rules of the circuit design; processor means for performing a functional decomposition of the input directives into primitive functions to perform the directives, establishing a primary iteration level for each directive, organizing the primitive functions based on data flow dependency, said processor means further generating an application program representative of the primitive functions by grouping together in clusters design rule checks and mask analysis operations that use a same base shape level and establishing within each cluster a set of lists of shape instances (LISAs) required to perform design checks, each cluster having a common base level and the LISAs representing VLSI design component instances necessary to perform input directives on a circuit design represented by the hierarchical circuit design data in said storage means; and accessing means for accessing the hierarchical circuit design from the storage means; said processor means receiving design components to be verified from said accessing means and performing intrusion searches on the design components and running said application program to process LISAs for each checking cluster and to dispatch checking functions based on intrusions detected.

Claim 16

A computer system for verifying a physical design of a very large scale integrated (VLSI) circuit expressed in the form of hierarchical circuit design data, comprising: storage means for storing the hierarchical circuit design data; input means for receiving, a set of directives to be performed on the hierarchical circuit design data, the input directives embodying design rule definitions for use in verifying compliance with design rules of the circuit design; processor means for performing a functional decomposition of the input directives into primitive functions to perform the directives, establishing a primary iteration level for each directive, organizing the primitive functions based on data flow dependency, said processor means further generating an application program representative of the primitive functions by grouping together in clusters design rule checks and mask analysis operations that use a same base shape level and establishing within each cluster a set of lists of shape instances (LISAs) required to perform design checks, each cluster having a common base level and the LISAs representing VLSI design component instances necessary to perform input directives on a circuit design represented by the hierarchical circuit design data in said storage means; and accessing means for accessing the hierarchical circuit design from the storage means; said processor means receiving design components to be verified from said accessing means and performing intrusion searches on the design components and running said application program to process LISAs for each checking cluster and to dispatch checking functions based on intrusions detected.