US5773882A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Seminconductor package
Assignee: Toshiba Corp
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Filing: 1997-02-21
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Granted: 1998-06-30
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Expires: 2017-02-21
Abstract
Abstract The first semiconductor package comprises a board equipped wiped with a wiring circuit including a connection on a main surface, a semiconductor chip mounted face down having input/output terminal corresponding to the connection of the board, flat external connector terminals leading to and are exposed on the other main surface of the board, and filled via hole connection to be electrically connected to the wiring circuit through a filled via hole installed right above each external connector terminal. Further, the second semiconductor package utilizes the above-described construction but the flat external connector terminals are led to and exposed on the other main surface of the board in a constant-pitch lattice-array.
Inventors
- 👤 Hiroshi Iwasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:24
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W70/65; H10W70/67; H10W70/68; H10W70/685; H10W70/699; H10W72/00; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/073; H10W72/07351; H10W72/07353; H10W72/20; H10W72/251; H10W72/252; H10W72/30; H10W72/331; H10W72/334; H10W72/851; H10W72/853; H10W72/856; H10W72/90; H10W72/931; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
177 words
A semiconductor package comprising: a single layer board having oppositely facing first and second main surfaces; a plurality of connection pads and a corresponding plurality of circuit wires on the first main surface, each of the circuit wires extending from a connection pad to a connection end, the circuit wires being disposed in a region of the first main surface; a semiconductor chip mounted on the first main surface and having input/output terminals aligned with and connected to the connection pads, the semiconductor chip being located over the circuit wires in the region of the first main surface; a plurality of flat external connector terminals exposed on the second main surface of said board, said external connector terminals being arrayed at constant pitch in a rectangular grid; and a filled via hole connection extending vertically from each of said external connector terminals and electrically connected to the connection end of each of said circuit wires, respectively; whereby each of said input/output terminals is connected by one of said circuit wires to one of said external connector terminals.
Claim 2
Dependent Claim
177 words
A semiconductor package comprising: a single layer board having oppositely facing first and second main surfaces; a plurality of connection pads and a corresponding plurality of circuit wires on the first main surface, each of the circuit wires extending from a connection pad to a connection end, the circuit wires being disposed in a region of the first main surface; a semiconductor chip mounted on the first main surface and having input/output terminals aligned with and connected to the connection pads, the semiconductor chip being located over the circuit wires in the region of the first main surface; a plurality of flat external connector terminals exposed on the second main surface of said board, said external connector terminals being arrayed at constant pitch in a rectangular grid; and a filled via hole connection extending vertically from each of said external connector terminals and electrically connected to the connection end of each of said circuit wires, respectively; whereby each of said input/output terminals is connected by one of said circuit wires to one of said external connector terminals.
Claim 3
Dependent Claim
38 words
A semiconductor package as set forth in claim 1, wherein the circuit wires are approximately flush with the main surface of the board, and including a resin layer filled between the single layer board and the semiconductor chip.
Claim 4
Dependent Claim
37 words
A semiconductor package as set forth in claim 1, wherein the circuit wires are in a wiring circuit region and including a dummy pattern installed for reinforcing the edges of the board enclosing said wiring circuit region.
Claim 5
Dependent Claim
20 words
A semiconductor package as set forth in claim 1 including dummy connector terminals in addition to said external connector terminals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |