Patent US5773862A successfully refreshed from Google Patents.
US5773862A
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Floating gate FGPA cell with separated select device
Assignee: Microsemi SoC Corp
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Filing: 1996-08-27
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Granted: 1998-06-30
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Expires: 2016-08-27
Abstract
Abstract The present invention provides for a programming portion of an FPGA cell of an integrated circuit and a process of manufacturing the programming portion. The programming portion has an EPROM transistor and a separated select transistor with the gate of the select transistor connected to the control gate of the EPROM transistor. Both transistors share a common N+ source/drain region, which is self-aligned with the gates of both transistors. With the select transistor separated from the EPROM transistor and the self-aligned common N+ region, the threshold voltage V T of the select transistor can be set precisely. This allows good control over the programming voltage for the control gate of the EPROM transistor and the time to program the floating gate of the EPROM transistor.
Inventors
- 👤 Jack Zezhong Peng
- 👤 Robert M. Salter, III
- 👤 Robert J. Lipp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:23
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10B; H10B41/00; H10B41/30; H10B41/35; H10B69/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
143 words
A programming portion of an FPGA cell in a substrate of an integrated circuit, comprising a first-type dopant region in said substrate and extending to a principal surface of said substrate; first, second and third second-type dopant regions in said first-type dopant region and extending to said principal surface; a floating gate electrode over a first channel region at said principal surface, said first channel region separating first and second second-type dopant regions; a control gate electrode over said floating gate; and a select transistor gate electrode over a second channel region at said principal surface, said second channel region separating said second and third second-type dopant regions, said select transistor gate electrode connected to said control sate electrode, wherein said second second-type region is substantially defined by an edge of said floating gate electrode and an edge of said control gate electrode.
Claim 2
Dependent Claim
143 words
A programming portion of an FPGA cell in a substrate of an integrated circuit, comprising a first-type dopant region in said substrate and extending to a principal surface of said substrate; first, second and third second-type dopant regions in said first-type dopant region and extending to said principal surface; a floating gate electrode over a first channel region at said principal surface, said first channel region separating first and second second-type dopant regions; a control gate electrode over said floating gate; and a select transistor gate electrode over a second channel region at said principal surface, said second channel region separating said second and third second-type dopant regions, said select transistor gate electrode connected to said control sate electrode, wherein said second second-type region is substantially defined by an edge of said floating gate electrode and an edge of said control gate electrode.
Claim 3
Dependent Claim
28 words
The programming portion of the FPGA cell of claim 1 wherein said floating gate electrode and said control gate electrode are laterally coextensive over said first channel region.
Claim 4
Dependent Claim
26 words
The programming portion of the FPGA cell of claim 2 wherein a single polysilicon layer comprises said control gate electrode and said select transistor gate electrode.
Claim 5
Dependent Claim
80 words
The programming portion of the FPGA cell of claim 1 further comprises a first gate oxide layer between said floating gate electrode and said first channel region, a second gate oxide layer between said select transistor gate electrode and said second channel region, said first gate oxide layer and said second gate oxide layer each having thicknesses unrelated to the thickness of the other gate oxide layer so that operations in said first channel and said second channel are optimized.
Claim 6
Dependent Claim
36 words
The programming portion of the FPGA cell of claim 4 wherein said first gate oxide layer has a thickness of approximately 100-180 Å and said second gate oxide layer has a thickness of approximately 200-400 Å.
Claim 7
Dependent Claim
189 words
In an FPGA cell having an interconnect transistor having first and second source/drains connected to first and second circuit nodes respectively, a floating gate electrode for turning said interconnect MOS transistor off and on responsive to the amount of charge on said floating gate electrode, and a portion for programming charge onto said floating gate electrode, said portion comprising a first-type dopant region in said substrate and extending to a principal surface of said substrate; first, second and third second-type dopant regions in said first-type dopant region and extending to said principal surface; said floating gate electrode extending over a first channel region at said principal surface, said first channel region separating first and second second-type dopant regions; a control gate electrode over said floating gate electrode; and a select transistor gate electrode over a second channel region at said principal surface, said second channel region separating said second and third second-type dopant regions, said select transistor gate electrode connected to said control gate electrode, wherein said second second-type region is substantially defined by an edge of said floating gate electrode and an edge of said control gate electrode.
Claim 8
Dependent Claim
189 words
In an FPGA cell having an interconnect transistor having first and second source/drains connected to first and second circuit nodes respectively, a floating gate electrode for turning said interconnect MOS transistor off and on responsive to the amount of charge on said floating gate electrode, and a portion for programming charge onto said floating gate electrode, said portion comprising a first-type dopant region in said substrate and extending to a principal surface of said substrate; first, second and third second-type dopant regions in said first-type dopant region and extending to said principal surface; said floating gate electrode extending over a first channel region at said principal surface, said first channel region separating first and second second-type dopant regions; a control gate electrode over said floating gate electrode; and a select transistor gate electrode over a second channel region at said principal surface, said second channel region separating said second and third second-type dopant regions, said select transistor gate electrode connected to said control gate electrode, wherein said second second-type region is substantially defined by an edge of said floating gate electrode and an edge of said control gate electrode.
Claim 9
Dependent Claim
28 words
The programming portion of the FPGA cell of claim 6 wherein said floating gate electrode and said control gate electrode are laterally coextensive over said first channel region.
Claim 10
Dependent Claim
26 words
The programming portion of the FPGA cell of claim 7 wherein a single polysilicon layer comprises said control gate electrode and said select transistor gate electrode.
Claim 11
Dependent Claim
80 words
The programming portion of the FPGA cell of claim 6 further comprises a first gate oxide layer between said floating gate electrode and said first channel region, a second gate oxide layer between said select transistor gate electrode and said second channel region, said first gate oxide layer and said second gate oxide layer each having thicknesses unrelated to the thickness of the other gate oxide layer so that operations in said first channel and said second channel are optimized.
Claim 12
Dependent Claim
36 words
The programming portion of the FPGA cell of claim 9 wherein said first gate oxide layer has a thickness of approximately 100-180 Å and said second gate oxide layer has a thickness of approximately 200-400 Å.
References Cited (Backward Citations)
US5569945A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |