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Patent US5773855A successfully refreshed from Google Patents.
US5773855A
Expired / Lapsed
US
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Microelectronic circuit including silicided field-effect transistor elements that bifunction as interconnects
Assignee: Bell Semiconductor LLC
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Filing: 1997-01-31
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Granted: 1998-06-30
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Expires: 2017-01-31
Abstract
Abstract Field-effect transistors are formed on a substrate having silicided elements including diffusion (source and drain) regions and polysilicon gates. The silicided surfaces of these elements have low ohmic resistance and are used to provide interconnection between contacts that are spaced from each other, thereby freeing routing areas for other interconnections. The diffusion regions of adjacent transistors have edges that face each other, and are formed with indentations which constitute portions of a substrate tap area. The low ohmic resistance of the silicided surfaces of the diffusion regions enables the substrate tap area to be cut out of the diffusion regions without degrading the electrical performance of the transistors, thereby providing a substantial reduction in the space required for the transistors on the substrate.
Inventors
- 👤 Michael Colwell
- 👤 Gary Cheung
- 👤 Paul Torgerson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
95 words
A microelectronic circuit, comprising: a substrate; a first field effect transistor that is formed on the substrate and includes a diffusion region constituting a source or drain, said diffusion region having a first surface that is silicided, said first silicided surface comprising a first region and a second region; and a first electrical contact within said first region, such that said silicided surface provides an electrical interconnection between said first contact and said second region thereby facilitating collection of electrical current across the first and second regions within the diffusion region to the electrical contact.
Claim 2
Dependent Claim
95 words
A microelectronic circuit, comprising: a substrate; a first field effect transistor that is formed on the substrate and includes a diffusion region constituting a source or drain, said diffusion region having a first surface that is silicided, said first silicided surface comprising a first region and a second region; and a first electrical contact within said first region, such that said silicided surface provides an electrical interconnection between said first contact and said second region thereby facilitating collection of electrical current across the first and second regions within the diffusion region to the electrical contact.
Claim 3
Dependent Claim
36 words
A circuit as in claim 1: further comprising a power rail that extends over the first field effect transistor; in which said first and second regions are disposed on laterally opposite sides of the rail respectively.
Claim 4
Dependent Claim
113 words
A circuit as in claim 1 further comprising: a second field effect transistor having first and second portions constituting a second drain and a second source, said second portion of said second field effect transistor having a second surface that is silicided: wherein said first and second silicided surfaces each define a periphery having indentations which face each other respectively, each indentation defining a respective indentation area; the circuit further comprises a substrate tap area that is formed at least partially within said indentation areas, said substrate tap area including a substrate tap for providing electrical contact to the substrate; and said first and second transistors are interconnected to form integrated circuit logic.
Claim 5
Dependent Claim
30 words
A circuit as in claim 3, further comprising a power rail that extends over the first and second field effect transistors and is ohmically connected to said substrate tap area.
Claim 6
Dependent Claim
92 words
A microelectronic circuit, comprising: a substrate; first and second transistors formed on the substrate, said transistors including silicided diffusion regions, each diffusion region constituting a source or a drain, each diffusion region defined by a horizontal periphery having an indentation such that the first transistor diffusion region indentation faces the second transistor diffusion region indentation, each indentation defining a respective indentation area; and a substrate tap area that is formed at least partially within said indentation areas, said substrate tap area including a substrate tap for providing electrical contact to the substrate.
Claim 7
Dependent Claim
92 words
A microelectronic circuit, comprising: a substrate; first and second transistors formed on the substrate, said transistors including silicided diffusion regions, each diffusion region constituting a source or a drain, each diffusion region defined by a horizontal periphery having an indentation such that the first transistor diffusion region indentation faces the second transistor diffusion region indentation, each indentation defining a respective indentation area; and a substrate tap area that is formed at least partially within said indentation areas, said substrate tap area including a substrate tap for providing electrical contact to the substrate.
Claim 8
Dependent Claim
28 words
A circuit as in claim 5, further comprising a power rail that extends over the first and second transistors and is ohmically connected to said substrate tap area.
Claim 9
Independent Claim
141 words
A method of providing an electrical interconnection for gate array field effect transistors formed on a substrate, comprising the steps of: (a) forming a first gate array field effect transistor on said substrate as comprising a first gate and a first diffusion region, the first diffusion region constituting a source or drain, said first diffusion region including first and second portions thereof, said first portion of said first diffusion region including a first electrical contact; (b) siliciding a surface of the first and second portions of the first diffusion region, such that said silicided surface provides a low resistance electrical interconnection between the electrical contact and the second portion of the first diffusion region, thereby facilitating collection of electrical current across the first diffusion region to the electrical contact; (c) ohmically connecting said first electrical contact to an external routing line.
Claim 10
Independent Claim
141 words
A method of providing an electrical interconnection for gate array field effect transistors formed on a substrate, comprising the steps of: (a) forming a first gate array field effect transistor on said substrate as comprising a first gate and a first diffusion region, the first diffusion region constituting a source or drain, said first diffusion region including first and second portions thereof, said first portion of said first diffusion region including a first electrical contact; (b) siliciding a surface of the first and second portions of the first diffusion region, such that said silicided surface provides a low resistance electrical interconnection between the electrical contact and the second portion of the first diffusion region, thereby facilitating collection of electrical current across the first diffusion region to the electrical contact; (c) ohmically connecting said first electrical contact to an external routing line.
Claim 11
Dependent Claim
46 words
A method as in claim 7, further comprising the step of: (c) forming a power rail that extends over the first field effect transistor such that said first and second portions of said first diffusion region are disposed on laterally opposite sides of the rail respectively.
Claim 12
Dependent Claim
126 words
A method as in claim 7 further comprising the step: (c) forming a second gate array field effect transistor on said substrate as comprising a second gate and a second diffusion region constituting a source or a drain, the second diffusion region having a surface that is silicided; the first and second diffusion regions each defined by a horizontal periphery having an indentation, each indentation defining an indentation area, the indentations facing each other respectively; such that said indentation areas constitute portions of a substrate tap area that is formed at least partially within said indentation areas, said substrate tap area including a substrate tap for providing electrical contact to the substrate; and interconnecting said first and second field effect transistors to form integrated circuit logic.
Claim 13
Dependent Claim
31 words
A method as in claim 9, further comprising the step of: (c) forming a power rail on the substrate that extends over and is ohmically connected to said substrate tap area.
Claim 14
Independent Claim
108 words
A method of fabricating a microelectronic circuit, comprising: (a) providing a substrate; (b) forming first and second transistors on the substrate, the first transistor having a first silicided diffusion region constituting a first source or drain, the second transistor having a second silicided diffusion region constituting a second source or drain, each silicided diffusion region defined bv a respective horizontal periphery, the peripheries having indentations which face each other respectively on the substrate; (c) providing a substrate tap at least partially within each indentation, the substrate tap electrically connecting the substrate to a voltage supply; and (d) interconnecting said first and second transistors to form integrated circuit logic.
Claim 15
Independent Claim
108 words
A method of fabricating a microelectronic circuit, comprising: (a) providing a substrate; (b) forming first and second transistors on the substrate, the first transistor having a first silicided diffusion region constituting a first source or drain, the second transistor having a second silicided diffusion region constituting a second source or drain, each silicided diffusion region defined bv a respective horizontal periphery, the peripheries having indentations which face each other respectively on the substrate; (c) providing a substrate tap at least partially within each indentation, the substrate tap electrically connecting the substrate to a voltage supply; and (d) interconnecting said first and second transistors to form integrated circuit logic.
Claim 16
Dependent Claim
36 words
A method as in claim 1, further comprising the step of: (c) forming a power rail on the substrate that extends over the first and second transistors and is ohmically connected to said substrate tap area.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |