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US5773362A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing an integrated ULSI heatsink

Assignee: International Business Machines Corp
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Filing: 1997-04-09
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Granted: 1998-06-30
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Expires: 2017-04-09
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Abstract

Abstract A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips. The heatsink itself is prepared by first optionally roughening the surface and metalizing the backside of the heatsink with metal interlayer. Next, the chip is thermally attached to the heatsink by reflowing the thermally conductive reflowable material.

Inventors

  • 👤 William R. Tonti
  • 👤 Jack A. Mandelman
  • 👤 Jerzy M. Zalesinski
  • 👤 Toshiharu Furukawa
  • 👤 Son V. Nguyen
  • 👤 Dureseti Chidambarrao

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 11:41
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/013; H10D; H10D62/00; H10D62/10; H10D62/117; H10D62/50; H10D62/57; H10W40/00; H10W40/20; H10W40/22; H10W72/019; H10W72/01961; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336; H10W72/07351; H10W72/07353; H10W72/30; H10W72/331; H10W72/334; H10W72/50; H10W72/59; H10W72/851; H10W72/874; H10W72/877; H10W72/90; H10W72/931; H10W74/00; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/751; H10W90/756; Y; Y10; Y10S; Y10S438/00; Y10S438/928; Y10S438/964

Claims Analysis

Total Claims: 20
Claim 1
Independent Claim 102 words
A method for fabricating a high power integrated package of an integrated circuit and a heatsink, comprising the steps of: fabricating an integrated circuit wafer up to dicing the wafer into chips; roughening a backside of the wafer to form an irregular surface, applying a metal to the roughened backside of the wafer; depositing a thermally conductive reflowable material on the metal applied to the backside of the wafer; dicing the wafer into chips; and thermally attaching a chip to a heatsink by reflowing the thermally conductive reflowable material to form a mechanical and thermal bond between the chip and the heatsink.
Claim 2
Independent Claim 102 words
A method for fabricating a high power integrated package of an integrated circuit and a heatsink, comprising the steps of: fabricating an integrated circuit wafer up to dicing the wafer into chips; roughening a backside of the wafer to form an irregular surface, applying a metal to the roughened backside of the wafer; depositing a thermally conductive reflowable material on the metal applied to the backside of the wafer; dicing the wafer into chips; and thermally attaching a chip to a heatsink by reflowing the thermally conductive reflowable material to form a mechanical and thermal bond between the chip and the heatsink.
Claim 3
Dependent Claim 25 words
The method recited in claim 1 wherein the step of roughening is performed by etching the backside of the wafer with high pressure inert particles.
Claim 4
Dependent Claim 21 words
The method recited in claim 1 wherein the step of roughening is performed by pattern etching the backside of the wafer.
Claim 5
Dependent Claim 29 words
The method recited in claim 1 wherein the step of roughening is performed by deposition of a porous material through which an irregular thermally conductive crystalline-like structure is grown.
Claim 6
Dependent Claim 23 words
The method recited in claim 1 wherein the step of roughening is performed by a random screening process to deposit an irregular mask.
Claim 7
Dependent Claim 23 words
The method recited in claim 1 wherein the step of coating the wafer backside comprises sequential evaporation of at least two metal interlayers.
Claim 8
Dependent Claim 21 words
The method recited in claim 6 wherein the metal interlayers are a coating of aluminum followed by a coating of chromium.
Claim 9
Dependent Claim 21 words
The method recited in claim 7 further comprising coating the metal interlayers with copper before depositing the thermally conductive reflowable material.
Claim 10
Dependent Claim 29 words
The method recited in claim 7 wherein the aluminum is deposited to a thickness of 5 to 10 μm and the chromium to a thickness of approximately 0.2 μm.
Claim 11
Dependent Claim 32 words
The method recited in claim 7 further comprising the steps of: depositing an aluminum layer over the metal interlayers to fill voids in the roughened wafer backside; and planarizing the aluminum layer.
Claim 12
Dependent Claim 25 words
The method recited in claim 1 further comprising the step of gettering the roughened wafer backside to remove any impurities before coating with said metal.
Claim 13
Independent Claim 31 words
The method recited in clam 1 further comprising the step of roughening a mating surface, to form an irregular surface, of said heatsink prior to attaching the chip to the heatsink.
Claim 14
Independent Claim 31 words
The method recited in clam 1 further comprising the step of roughening a mating surface, to form an irregular surface, of said heatsink prior to attaching the chip to the heatsink.
Claim 15
Dependent Claim 23 words
The method recited in claim 12 further comprising the step of plating the roughened mating surface of said heatsink with a metal interlayer.
Claim 16
Dependent Claim 16 words
The method recited in claim 13 wherein the metal interlayer plated on the heatsink is chromium.
Claim 17
Dependent Claim 22 words
The method recited in claim 14 further comprising the step of sputtering a copper coating over the chromium interlayer on the heatsink.
Claim 18
Dependent Claim 25 words
The method of claim 15 wherein the step of applying a metal to the wafer backside comprises sequential evaporation of at least two metal interlayers.
Claim 19
Dependent Claim 20 words
The method of claim 16 further comprising coating the metal interlayers with copper before depositing the thermally conductive reflowable material.
Claim 20
Dependent Claim 22 words
The method of claim 17 further comprising the step of plating the roughened mating surface of said heatsink with a metal interlayer.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-06-29 2001-12-29 2002-06-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-06-29 2005-12-29 2006-06-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-06-29 2009-12-29 2010-06-30 $7700.00 Window Closed / Lapsed

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