Method and system for interchanging operands during complex instruction execution in a data processing system

Claim 3

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 1 wherein said first field is coupled to an output of a first multiplexer and said second field is coupled to an output of a second multiplexer, and wherein an input to said first multiplexer is coupled to said second field and an input to said second multiplexer is coupled to said first field, and wherein said step of interchanging said first operand pointer in said first field with said second operand pointer in said second field includes moving said first operand pointer to said second field via said second multiplexer and moving said second operand pointer to said first field via said first multiplexer.

Claim 4

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 1 further including the steps of: detecting the presence of a complex instruction in said instruction queue in said execution unit; in response to detecting said complex instruction, executing an alternate instruction to produce an intermediate result; temporarily storing said intermediate result in a rename buffer designated by a rename buffer pointer stored in a rename buffer pointer field in said instruction; interchanging said first operand pointer in said first field with said rename buffer pointer in said rename buffer pointer field; and loading into said first operand register a value stored in said rename buffer designated by said rename buffer pointer stored in said first field.

Claim 5

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 3 wherein said first field is coupled to an output of a first multiplexer and said rename buffer pointer field is coupled to an output of a second multiplexer, and wherein an input to said first multiplexer is coupled to said rename buffer pointer field and an input to said second multiplexer is coupled to said first field, and wherein said step of interchanging said first operand pointer in said first field with said rename buffer pointer in said rename buffer pointer field includes moving said first operand pointer to said rename buffer pointer field via said second multiplexer and moving said rename buffer pointer to said first field via said first multiplexer.

Claim 6

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 4 wherein said execution unit includes an algorithmic state machine coupled to said first and second multiplexers for communicating control signals to control execution of an algorithm that synthesizes a complex instruction, and wherein said step of moving said first operand pointer to said second field via said second multiplexer and moving said second operand pointer to said first field via said first multiplexer includes: setting said first multiplexer to output said rename buffer pointer in response to receiving said control signals; setting said second multiplexer to output said first operand pointer in response to receiving said control signals; and moving said first operand pointer to said rename buffer pointer field via said second multiplexer and moving said rename buffer pointer to said first field via said first multiplexer, in response to said control signals from said algorithmic state machine.

Claim 7

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 2 wherein said execution unit includes an algorithmic state machine coupled to said first and second multiplexers for communicating control signals to control execution of an algorithm that synthesizes a complex instruction, and wherein said step of moving said first operand pointer to said second field via said second multiplexer and moving said second operand pointer to said first field via said first multiplexer includes: setting said first multiplexer to output said second operand pointer in response to receiving said control signals; setting said second multiplexer to output said first operand pointer in response to receiving said control signals; and moving said first operand pointer to said second field via said second multiplexer and moving said second operand pointer to said first field via said first multiplexer, in response to said control signals from said algorithmic state machine.

Claim 8

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 1 further including the steps of: loading an instruction into said instruction queue, said instruction having said plurality of fields, wherein: a third field contains a third operand pointer for designating a value stored in a rename buffer register file for loading into said first operand register; and a fourth field contains a fourth operand pointer for designating a value stored in said rename buffer register file for loading into said second operand register; and interchanging said third operand pointer in said third field with said fourth operand pointer in said fourth field in response to interchanging said first operand pointer in said first field with said second operand pointer in said second field.

Claim 9

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 7 further including the steps of: loading an instruction into said instruction queue, said instruction having said plurality of fields, wherein: a fifth field contains a first bit for selecting either said first operand pointer or said third operand pointer for designating one of two values for loading into said first operand register; and a sixth field contains a second bit for selecting either said second operand pointer or said fourth operand pointer for designating one of two values for loading into said second operand register; and interchanging said first bit in said fifth field with said second bit in said sixth field in response to interchanging said first operand pointer in said first field with said second operand pointer in said second field.

Claim 10

The method for interchanging operands and loading said operands into a plurality of operand registers according to claim 3 wherein said step of temporarily storing said intermediate result in a rename buffer designated by a rename buffer pointer stored in a rename buffer pointer field in said instruction includes temporarily storing said intermediate result in a rename buffer designated by a target rename buffer pointer stored in a target rename buffer pointer field in said instruction.

Claim 11

A data processing system for interchanging operands and loading said operands into a plurality of operand registers in an execution unit within said data processing system during execution of a complex instruction, wherein said execution unit includes an instruction queue, and wherein said execution unit executes atomic instructions and complex instructions having a plurality of operand pointers for pointing to said plurality of operands stored in a register file coupled to said operand registers, said data processing system comprising: means for determining whether an instruction is an atomic instruction or a complex instruction, means for storing said plurality of operands within said register file in response to a determination that said instruction is a complex instruction, wherein said plurality of operands includes a first operand and a second operand; means for loading said complex instruction into said instruction queue, said complex instruction having a plurality of fields, wherein: a first field contains a first operand pointer for designating a value stored in said register file for loading into a first operand register; and a second field contains a second operand pointer for designating a value stored in said register file for loading into a second operand register; means for interchanging said first operand pointer in said first field with said second operand pointer in said second field; means for loading into said first operand register a value stored in said register file designated by said second operand pointer stored in said first field; and means for loading into said second operand register a value stored in said register file designated by said first operand pointer stored in said second field, wherein values in said register file designated by operand pointers in said fields of said complex instruction are loaded into different operand registers than originally specified by said complex instruction during execution of said complex instruction.

Claim 12

A data processing system for interchanging operands and loading said operands into a plurality of operand registers in an execution unit within said data processing system during execution of a complex instruction, wherein said execution unit includes an instruction queue, and wherein said execution unit executes atomic instructions and complex instructions having a plurality of operand pointers for pointing to said plurality of operands stored in a register file coupled to said operand registers, said data processing system comprising: means for determining whether an instruction is an atomic instruction or a complex instruction, means for storing said plurality of operands within said register file in response to a determination that said instruction is a complex instruction, wherein said plurality of operands includes a first operand and a second operand; means for loading said complex instruction into said instruction queue, said complex instruction having a plurality of fields, wherein: a first field contains a first operand pointer for designating a value stored in said register file for loading into a first operand register; and a second field contains a second operand pointer for designating a value stored in said register file for loading into a second operand register; means for interchanging said first operand pointer in said first field with said second operand pointer in said second field; means for loading into said first operand register a value stored in said register file designated by said second operand pointer stored in said first field; and means for loading into said second operand register a value stored in said register file designated by said first operand pointer stored in said second field, wherein values in said register file designated by operand pointers in said fields of said complex instruction are loaded into different operand registers than originally specified by said complex instruction during execution of said complex instruction.

Claim 13

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 10 wherein said first field is coupled to an output of a first multiplexer and said second field is coupled to an output of a second multiplexer, and wherein an input to said first multiplexer is coupled to said second field and an input to said second multiplexer is coupled to said first field, and wherein said means for interchanging said first operand pointer in said first field with said second operand pointer in said second field includes means for moving said first operand pointer to said second field via said second multiplexer and means for moving said second operand pointer to said first field via said first multiplexer.

Claim 14

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 10 further including: means for detecting the presence of a complex instruction in said instruction queue in said execution unit; means for executing an alternate instruction to produce an intermediate result in response to detecting said complex instruction; means for temporarily storing said intermediate result in a rename buffer designated by a rename buffer pointer stored in a rename buffer pointer field in said instruction; means for interchanging said first operand pointer in said first field with said rename buffer pointer in said rename buffer pointer field; and means for loading into said first operand register a value stored in said rename buffer designated by said rename buffer pointer stored in said first field.

Claim 15

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 12 wherein said first field is coupled to an output of a first multiplexer and said rename buffer pointer field is coupled to an output of a second multiplexer, and wherein an input to said first multiplexer is coupled to said rename buffer pointer field and an input to said second multiplexer is coupled to said first field, and wherein said means for interchanging said first operand pointer in said first field with said rename buffer pointer in said rename buffer pointer field includes means for moving said first operand pointer to said rename buffer pointer field via said second multiplexer and means for moving said rename buffer pointer to said first field via said first multiplexer.

Claim 16

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 13 wherein said execution unit includes an algorithmic state machine coupled to said first and second multiplexers for communicating control signals to control execution of an algorithm that synthesizes a complex instruction, and wherein said means for moving said first operand pointer to said second field via said second multiplexer and means for moving said second operand pointer to said first field via said first multiplexer includes: means for setting said first multiplexer to output said rename buffer pointer in response to receiving said control signals; means for setting said second multiplexer to output said first operand pointer in response to receiving said control signals; and means for moving said first operand pointer to said rename buffer pointer field via said second multiplexer and moving said rename buffer pointer to said first field via said first multiplexer, in response to said control signals from said algorithmic state machine.

Claim 17

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 11 wherein said execution unit includes an algorithmic state machine coupled to said first and second multiplexers for communicating control signals to control execution of an algorithm that synthesizes a complex instruction, and wherein said means for moving said first operand pointer to said second field via said second multiplexer and means for moving said second operand pointer to said first field via said first multiplexer includes: means for setting said first multiplexer to output said second operand pointer in response to receiving said control signals; means for setting said second multiplexer to output said first operand pointer in response to receiving said control signals; and means for moving said first operand pointer to said second field via said second multiplexer and means for moving said second operand pointer to said first field via said first multiplexer in response to said control signals from said algorithmic state machine.

Claim 18

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 10 further including: means for loading an instruction into said instruction queue, said instruction having said plurality of fields, wherein: a third field contains a third operand pointer for designating a value stored in a rename buffer register file for loading into said first operand register; and a fourth field contains a fourth operand pointer for designating a value stored in said rename buffer register file for loading into said second operand register; and means for interchanging said third operand pointer in said third field with said fourth operand pointer in said fourth field in response to interchanging said first operand pointer in said first field with said second operand pointer in said second field.

Claim 19

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 16 further including: means for loading an instruction into said instruction queue, said instruction having said plurality of fields, wherein: a fifth field contains a first bit for selecting either said first operand pointer or said third operand pointer for designating one of two values for loading into said first operand register; and a sixth field contains a second bit for selecting either said second operand pointer or said fourth operand pointer for designating one of two values for loading into said second operand register; and means for interchanging said first bit in said fifth field with said second bit in said sixth field in response to interchanging said first operand pointer in said first field with said second operand pointer in said second field.

Claim 20

The data processing system for interchanging operands and loading said operands into a plurality of operand registers according to claim 12 wherein said means for temporarily storing said intermediate result in a rename buffer designated by a rename buffer pointer stored in a rename buffer pointer field in said instruction includes means for temporarily storing said intermediate result in a rename buffer designated by a target rename buffer pointer stored in a target rename buffer pointer field in said instruction.

Claim 23

A method in a data processing system for loading an operand into one of a plurality of operand registers according to claim 19 wherein said second pointer field is coupled to an output of a multiplexer, and wherein an input to said multiplexer is coupled to said first pointer field, and wherein said step of moving said operand pointer in said first pointer field to said second pointer field includes moving said operand pointer in said first pointer field to said second pointer field via said multiplexer.